How can PCB designers use topology planning and wiring tools to quickly complete PCB design?

This paper focuses on the PCB designers using IP, and further using topology planning and routing tools to support IP, quickly complete the entire PCB design. As you can see from Figure 1, the design engineer’s responsibility is to obtain the IP by laying out a small number of necessary components and planning critical interconnect paths between them. Once the IP is obtained, the IP information can be provided to PCB designers who do the rest of the design.


How can PCB designers use topology planning and wiring tools to quickly complete PCB design

Figure 1: Design engineers get IP, PCB designers further use topology planning and wiring tools to support IP, quickly complete the entire PCB design.

Instead of having to go through a process of interaction and iteration between design engineers and PCB designers to get the correct design intent, the design engineers already get this information and the results are fairly accurate, which helps PCB designers a lot. In many designs, design engineers and PCB designers do interactive layout and wiring, which consumes valuable time on both sides. Historically, interactivity is necessary, but time-consuming and inefficient. The initial plan provided by the design engineer may be just a manual drawing without proper components, bus width, or pin output cues.

While engineers using topology planning techniques can capture the layout and interconnections of some components as PCB designers become involved in the design, the design may require the layout of other components, capture other IO and bus structures, and all interconnections.

PCB designers need to adopt topology planning and interact with laid out and unlaid components to achieve optimal layout and interaction planning, thereby improving PCB design efficiency.

After critical and high-density areas are laid out and the topology planning is obtained, the layout may be completed before the final topology planning. Therefore, some topology paths may have to work with the existing layout. Although they are of lower priority, they still need to be connected. Thus part of the planning was generated around the layout of the components. In addition, this level of planning may require more detail to give the necessary priority to other signals.

Detailed topology planning

Figure 2 shows a detailed layout of the components after they are laid out. The bus has 17 bits in total, and they have a fairly well-organized signal flow.


How can PCB designers use topology planning and wiring tools to quickly complete PCB design

Figure 2: Network lines for these buses are the result of topology planning and layout with a higher priority.

To plan this bus, PCB designers need to consider existing barriers, layer design rules, and other important constraints. With these conditions in mind, they mapped out a topology path for the bus as shown in Figure 3.

How can PCB designers use topology planning and wiring tools to quickly complete PCB design

Figure 3: The planned bus.

In Figure 3, detail “1” lays out the component pins on the top layer of “red” for the topological path leading from the component pins to detail “2”. The unencapsulated area used for this part, and only the first layer is identified as the cabling layer. This seems obvious from a design point of view, and the routing algorithm will use the topological path with the top layer connected to red. However, some obstacles may provide the algorithm with other layer routing options before automatically routing this particular bus.

As the bus is organized into tight traces at the first layer, the designer begins to plan the transition to the third layer at detail 3, taking into account the distance the bus travels across the entire PCB. Note that this topological path on the third layer is wider than the top layer because of the extra space required to accommodate the impedance. In addition, the design specifies the exact location (17 holes) for the layer conversion.

As the topological path follows the right-center portion of Figure 3 to detail “4”, many single-bit T-shaped junctions need to be drawn from the topological path connections and individual component pins. The PCB designer’s choice is to keep most of the connection flow on layer 3 and through to other layers for connecting component pins. So they drew a topology area to indicate the connection from the main bundle to layer 4 (pink), and had these single-bit T-shaped contacts connect to layer 2 and then connect to the device pins using other through-holes.

Topological paths continue at level 3 to detail “5” to connect active devices. These connections are then connected from the active pins to a pull-down resistor below the active device. The designer uses another topology area to regulate connections from layer 3 to layer 1, where the component pins are divided into active devices and pull-down resistors.

This level of detailed planning took about 30 seconds to complete. Once this plan is captured, the PCB designer may want to immediately route or create further topology plans, and then complete all topology plans with automatic routing. Less than 10 seconds from the completion of the planning to the results of automatic wiring. The speed doesn’t really matter, and in fact it’s a waste of time if the designer’s intentions are ignored and the automatic wiring quality is poor. The following diagrams show the results of automatic wiring.

Topology Routing

Starting at the top left, all wires from the component pins are located on layer 1, as expressed by the designer, and compressed into a tight bus structure, as shown in Details “1” and “2” in Figure 4. The transition between level 1 and level 3 takes place in detail “3” and takes the form of a very space-consuming through-hole. Again, the impedance factor is taken into account, so the lines are wider and more spaced, as represented by the actual width path.

How can PCB designers use topology planning and wiring tools to quickly complete PCB design

Figure 4: Results of routing with topologies 1 and 3.

As shown in detail “4” in Figure 5, the topology path becomes larger due to the need to use holes to accommodate single-bit T-type junctions. Here the plan again reflects the designer’s intention for these single-bit T-type exchange points, wiring from layer 3 to layer 4. In addition, the trace on the third layer is very tight, although it expands a little at the insertion hole, it soon tights up again after passing the hole.

How can PCB designers use topology planning and wiring tools to quickly complete PCB design

Figure 5: Result of routing with detail 4 topology.

Figure 6 shows the result of automatic wiring at detail “5”. Active device connections at layer 3 require conversion to layer 1. The through-holes are arranged neatly above the component pins, and the layer 1 wire is connected to the active component first and then to the layer 1 pull-down resistor.

How can PCB designers use topology planning and wiring tools to quickly complete PCB design

Figure 6: The result of routing with the detail 5 topology.

The conclusion of the above example is that the 17 bits are detailed into four different device types, representing the designer’s intention for layer and path direction, which can be captured in about 30 seconds. Then high quality automatic wiring can be carried out, the required time is about 10 seconds.

By raising the level of abstraction from wiring to topology planning, the total interconnect time is greatly reduced, and designers have a really clear understanding of density and the potential to complete the design before the interconnect begins, such as why keep wiring at this point in the design? Why not go ahead with the planning and add wiring in the back? When will the full topology be planned? If the above example is considered, the abstraction of one plan can be used with another plan rather than with 17 separate networks with many line segments and many holes in each network, a concept that is particularly important when considering an Engineering Change Order (ECO).

Engineering Change Order (ECO)

In the following example, the FPGA pin output is incomplete. The design engineers have informed the PCB designers of this fact, but for schedule reasons, they need to advance the design as far as possible before the FPGA pin output is complete.

In the case of known pin output, PCB designer starts to plan the FPGA space, and at the same time, the designer should consider the leads from other devices to FPGA. The IO was planned to be on the right side of the FPGA, but now it is on the left side of the FPGA, causing the pin output to be completely different from the original plan. Because designers work at a higher level of abstraction, they can accommodate these changes by removing the overhead of moving all wiring around the FPGA and replacing it with topology path modifications.

However, it’s not just FPGas that are affected; These new pin outputs also affect the leads coming out of the related devices. The end of the path also moves in order to accommodate the flat-encapsulated lead entry path; Otherwise, twisted-pair cables will be twisted, wasting valuable space on the high-density PCB. Twisting for these bits requires extra space for wiring and perforations, which may not be met at the end of the design phase. If the schedule were tight, it would be impossible to make such adjustments to all of these routes. The point is that topology planning provides a higher level of abstraction, so implementing these ECOs is much easier.

The automatic routing algorithm that follows the designer’s intent sets a quality priority over a quantity priority. If a quality problem is identified, it is quite right to let the connection fail rather than produce a poor-quality wiring, for two reasons. First, it is easier to connect a failed connection than to clean up this wiring with bad results and other wiring operations that automate wiring. Second, the designer’s intent is carried out and the designer is left to determine the quality of the connection. However, these ideas are useful only if the connections of failed wiring are relatively simple and localized.

A good example is the inability of a cabler to achieve 100% planned connections. Instead of sacrificing quality, allow some planning to fail, leaving some unconnected wiring behind. All wires are routed by topology planning, but not all lead to component pins. This ensures that there is room for failed connections and provides a relatively easy connection.

This article summary

Topology planning is a tool that works with a digital signalized PCB design process and is easily accessible to design engineers, but it also has specific spatial, layer, and connection flow capabilities for complex planning considerations. PCB designers can use the topology planning tool at the beginning of the design or after the design engineer obtains their IP, depending on who is using this flexible tool to best fit their design environment.

Topology cablers simply follow the designer’s plan or intent to provide high-quality cabling results. Topology planning, when faced with ECO, is much faster to operate than separate connections, thus enabling the topology cabler to adopt ECO more quickly, providing fast and accurate results.