Through the analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. Gwada kada ku canza yadudduka na alamun sigina akan allon PCB, wato, gwada kada kuyi amfani da ta hanyar da ba dole ba.

4. Ya kamata a hako fitilun wuta da ƙasa a kusa, kuma gubar tsakanin via da fil ɗin ya kamata ya zama gajere kamar yadda zai yiwu, saboda za su ƙara inductance. A lokaci guda kuma, ikon da jagorancin ƙasa ya kamata ya kasance mai kauri kamar yadda zai yiwu don rage rashin ƙarfi.

5. Sanya wasu ƙasan ta hanyar kusa da ta siginar siginar don samar da madauki mafi kusa don siginar. Yana da ma yiwuwa a sanya ɗimbin yawa na ƙasa mara amfani ta hanyar a kan allon PCB. Tabbas, zane yana buƙatar zama mai sassauƙa. Samfurin da aka tattauna a baya shine yanayin inda akwai pads akan kowane Layer. Wani lokaci, muna iya rage ko ma cire pads na wasu yadudduka. Musamman lokacin da yawa na vias yana da yawa, yana iya haifar da samuwar tsagi mai karya wanda ke raba madauki a cikin Layer na jan karfe. Don magance wannan matsala, ban da motsi matsayi na via, za mu iya kuma la’akari da sanya via a kan tagulla Layer. An rage girman kushin.