In design, layout is an important part. The quality of the layout result will directly affect the effect of the wiring, so it can be considered that a reasonable layout is the first step to a successful PCB design. Especially the pre-layout is the process of thinking about the entire circuit board, signal flow, heat dissipation, structure and other structures. If the pre-layout fails, no amount of effort will be needed.

PCB layout design The design process flow of printed circuit boards includes schematic design, electronic component database registration, design preparation, block division, electronic component configuration, configuration confirmation, wiring and final inspection. In the process of the process, no matter which process is found to be a problem, it must be returned to the previous process for reconfirmation or correction.

Tsab ntawv xov xwm no ua ntej qhia txog PCB layout tsim cov cai thiab cov tswv yim, thiab tom qab ntawd piav qhia yuav ua li cas tsim thiab tshuaj xyuas PCB layout, los ntawm cov txheej txheem DFM cov cai, thermal tsim cov cai, cov kev cai ntawm kev ncaj ncees, EMC cov cai, txheej txheej thiab cov kev faib hluav taws xob hauv av, thiab lub zog modules. Cov kev xav tau thiab lwm yam yuav raug txheeb xyuas kom meej, thiab ua raws li tus kws kho kom paub cov ntsiab lus.

PCB layout txoj cai

1. Nyob rau hauv ib txwm muaj, tag nrho cov khoom yuav tsum tau teem rau tib qhov chaw ntawm lub rooj tsav xwm Circuit Court. Tsuas yog thaum cov khoom siv saum toj kawg nkaus yog tuab dhau lawm, qee cov khoom siv nrog qhov siab siab thiab tsis tshua muaj cua sov, xws li nti resistors, nti capacitors, thiab nti capacitors, yuav raug ntsia. Chip IC, thiab lwm yam yog muab tso rau hauv qab txheej.

2. Raws li qhov kev ua tau zoo ntawm kev ua haujlwm ntawm hluav taws xob, cov khoom siv yuav tsum tau muab tso rau ntawm daim phiaj thiab teem caij sib dhos los yog sib dhos rau ib leeg kom zoo nkauj thiab zoo nkauj. Raws li ib txwm muaj, cov khoom tsis raug tso cai sib tshooj; Kev npaj ntawm cov khoom yuav tsum yog compact, thiab cov khoom yuav tsum tau teem rau tag nrho cov layout. Kev faib tawm yog uniform thiab ntom.

3. The minimum distance between adjacent land patterns of different components on the circuit board should be above 1mm.

4. Qhov kev ncua deb ntawm ntug ntawm lub rooj tsav xwm Circuit Court feem ntau tsis tsawg dua 2MM. Qhov zoo tshaj plaws zoo ntawm lub rooj tsav xwm Circuit Court yog cov duab plaub, thiab qhov sib piv yog 3: 2 lossis 4: 3. Thaum qhov loj ntawm lub rooj tsav xwm Circuit Court loj dua 200MM los ntawm 150MM, xav txog seb lub rooj tsav xwm hauv Circuit Court tuaj yeem tiv taus lub zog siv tshuab.

PCB layout design skills

Hauv kev tsim qauv ntawm PCB, cov chav nyob ntawm lub rooj tsav xwm Circuit Court yuav tsum tau txheeb xyuas, thiab cov qauv tsim yuav tsum yog raws li qhov pib ua haujlwm. Thaum nteg tawm tag nrho cov khoom ntawm lub voj voog, cov hauv paus ntsiab lus hauv qab no yuav tsum tau ua raws:

1. Npaj txoj haujlwm ntawm txhua qhov kev ua haujlwm hauv Circuit Court raws li lub voj voog khiav, kom cov txheej txheem yooj yim rau cov teeb liab ncig, thiab cov teeb liab tau khaws cia rau tib qho kev taw qhia kom ntau li ntau tau [1].

2. Take the core components of each functional unit as the center and lay out around him. The components should be uniformly, integrally and compactly arranged on the PCB to minimize and shorten the leads and connections between the components.

3. Rau cov khoom siv hluav taws xob ua haujlwm ntawm cov khoom siv hluav taws xob siab, qhov kev faib tawm ntawm cov khoom yuav tsum raug txiav txim siab. Nyob rau hauv dav dav circuits, cov khoom yuav tsum tau teem nyob rau hauv parallel kom ntau li ntau tau, uas tsis yog tsuas yog zoo nkauj, tab sis kuj yooj yim rau nruab thiab yooj yim rau loj tsim.

Yuav tsim thiab tshuaj xyuas PCB li cas

1. DFM requirements for layout

1. Cov txheej txheem kev pom zoo tau raug txiav txim siab, thiab txhua yam khoom siv tau muab tso rau ntawm lub rooj tsavxwm.

2. The origin of the coordinates is the intersection of the left and lower extension lines of the board frame, or the lower left pad of the lower left socket.

3. The actual size of the PCB, the location of the positioning device, etc. are consistent with the process structure element map, and the device layout of the area with restricted device height requirements meets the requirements of the structure element map.

4. Txoj hauj lwm ntawm lub dial hloov, pib dua ntaus ntawv, qhov taw qhia lub teeb, thiab lwm yam yog qhov tsim nyog, thiab tus tuav tuav tsis cuam tshuam nrog cov khoom siv nyob ib puag ncig.

5. Cov txheej txheem sab nrauv ntawm lub rooj tsavxwm muaj cov radian du ntawm 197mil, los yog tsim raws li cov qauv duab loj.

6. Ordinary boards muaj 200mil txheej txheem npoo; sab laug thiab sab xis ntawm lub nraub qaum muaj cov txheej txheem npoo ntau dua 400mil, thiab sab sauv thiab sab qis muaj cov txheej txheem npoo ntau dua 680mil. Cov cuab yeej tso tawm tsis cuam tshuam nrog qhov qhib qhov rais.

7. All kinds of additional holes (ICT positioning hole 125mil, handle bar hole, elliptical hole and fiber holder hole) that need to be added are all missing and set correctly.

8. Cov cuab yeej tus pin suab, ntaus ntawv taw qhia, ntaus suab, ntaus ntawv qiv, thiab lwm yam uas tau ua tiav los ntawm yoj soldering coj mus rau hauv tus account qhov yuav tsum tau ntawm yoj soldering.

9. The device layout spacing meets the assembly requirements: surface mount devices are greater than 20mil, IC is greater than 80mil, and BGA is greater than 200mil.

10. Lub crimping qhov chaw muaj ntau tshaj 120 mils nyob rau hauv lub cheeb tsam ntawm qhov chaw, thiab tsis muaj ib tug ntaus ntawv nyob rau hauv lub dhau los ntawm lub crimping qhov chaw ntawm lub vuam nto.

11. Tsis muaj cov khoom siv luv luv ntawm cov khoom siv siab, thiab tsis muaj cov khoom siv patch thiab cov khoom siv luv luv thiab me me tau muab tso rau hauv 5 hli ntawm cov khoom siv nrog qhov siab siab tshaj 10mm.

12. Polar li muaj polarity silkscreen logos. X thiab Y cov lus qhia ntawm tib hom polarized plug-in Cheebtsam yog tib yam.

13. All devices are clearly marked, no P*, REF, etc. are not clearly marked.

14. Muaj 3 qhov chaw tus cursors rau ntawm qhov chaw uas muaj SMD cov cuab yeej, uas tau muab tso rau hauv “L” zoo li. Qhov kev ncua deb ntawm qhov nruab nrab ntawm qhov chaw tus cursor thiab ntug ntawm lub rooj tsavxwm yog ntau dua 240 mils.

15. Yog tias koj yuav tsum ua cov txheej txheem boarding, qhov kev teeb tsa raug txiav txim siab los pab txhawb kev tsav tsheb thiab PCB ua thiab sib dhos.

16. Lub chipped npoo (qhov txawv txav) yuav tsum tau ntim rau hauv cov milling grooves thiab stamp qhov. Lub qhov taub yog qhov tsis muaj hlau tsis muaj hlau, feem ntau 40 mils hauv txoj kab uas hla thiab 16 mils ntawm ntug.

17. The test points used for debugging have been added in the schematic diagram, and they are placed appropriately in the layout.

Qhov thib ob, thermal tsim cov cai ntawm cov txheej txheem

1. Heating components and exposed components of the casing are not in close proximity to wires and heat-sensitive components, and other components should also be properly kept away.

2. The placement of the radiator takes into account the convection problem, and there is no interference of high components in the projection area of ​​the radiator, and the range is marked on the mounting surface with silk screen.

3. Cov txheej txheem yuav siv sij hawm rau hauv tus account tsim nyog thiab du cov cua kub dissipation raws.

4. Lub tshuab electrolytic capacitor yuav tsum tau muab cais kom zoo los ntawm cov khoom siv hluav taws xob kub.

5. Xav txog cov cua kub dissipation ntawm cov khoom siv hluav taws xob siab thiab cov khoom siv hauv qab lub gusset.

Thib peb, lub teeb liab kev ncaj ncees yuav tsum tau ntawm lub layout

1. The start-end matching is close to the sending device, and the end matching is close to the receiving device.

2. Place decoupling capacitors close to related devices

3. Place crystals, crystal oscillators and clock drive chips close to related devices.

4. High-speed thiab low-speed, digital thiab analog yog teem nyias raws li modules.

5. Txiav txim siab cov qauv topological ntawm lub tsheb npav raws li kev soj ntsuam thiab simulation cov txiaj ntsig lossis cov kev paub dhau los los xyuas kom meej tias cov txheej txheem yuav tsum tau ua.

6. If it is to modify the board design, simulate the signal integrity problem reflected in the test report and give a solution.

7. The layout of the synchronous clock bus system meets the timing requirements.

Plaub, EMC cov cai

1. Inductive devices that are prone to magnetic field coupling, such as inductors, relays, and transformers, should not be placed close to each other. When there are multiple inductance coils, the direction is vertical and they are not coupled.

2. Txhawm rau kom tsis txhob muaj kev cuam tshuam ntawm electromagnetic cuam tshuam ntawm cov cuab yeej ntawm lub vuam nto ntawm ib lub rooj tsavxwm thiab ib lub rooj tsavxwm uas nyob ib sab, tsis muaj cov khoom siv rhiab heev thiab cov khoom siv hluav taws xob muaj zog yuav tsum muab tso rau ntawm qhov chaw vuam ntawm ib lub rooj tsavxwm.

3. The interface components are placed close to the edge of the board, and appropriate EMC protection measures have been taken (such as shielding shells, hollowing out of the power supply ground, etc.) to improve the EMC capability of the design.

4. Kev tiv thaiv Circuit Court yog muab tso rau ze ntawm lub interface Circuit Court, ua raws li lub hauv paus ntsiab lus ntawm kev tiv thaiv thawj zaug thiab ces lim.

5. Qhov kev ncua deb ntawm lub shielding lub cev thiab shielding plhaub mus rau lub shielding lub cev thiab shielding cover plhaub yog ntau tshaj 500 mils rau cov khoom uas muaj siab transmitting hwj chim los yog tshwj xeeb rhiab heev (xws li siv lead ua oscillators, crystals, thiab lwm yam).

6. A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong devices and signals.

Five, layer setting and power supply and ground division requirements

1. Thaum ob lub teeb liab txheej yog ncaj qha nyob ib sab ntawm ib leeg, txoj cai kab ntsug yuav tsum tau txhais.

2. Cov txheej txheem hluav taws xob tseem ceeb nyob ib sab ntawm nws cov txheej txheem hauv av kom ntau li ntau tau, thiab cov txheej txheem hluav taws xob ua tau raws li txoj cai 20H.

3. Each wiring layer has a complete reference plane.

4. Multi-txheej boards yog laminated thiab cov khoom tseem ceeb (CORE) yog symmetrical los tiv thaiv warping tshwm sim los ntawm unevenly faib ntawm tooj liab daim tawv nqaij ceev thiab asymmetrical thickness ntawm nruab nrab.

5. Lub thickness ntawm lub rooj tsavxwm yuav tsum tsis pub tshaj 4.5mm. Rau cov neeg uas muaj lub thickness ntau dua 2.5 hli (rov qab dav dua 3 hli), cov kws tshaj lij yuav tsum tau lees paub tias tsis muaj teeb meem nrog PCB ua, sib dhos, thiab cov khoom siv, thiab PC daim npav thickness yog 1.6 hli.

6. Thaum lub thickness-rau-diameter piv ntawm qhov siab tshaj 10: 1, nws yuav raug lees paub los ntawm PCB chaw tsim tshuaj paus.

7. The power and ground of the optical module are separated from other power and ground to reduce interference.

8. Lub zog thiab kev ua hauv av ntawm cov khoom tseem ceeb ua tau raws li qhov yuav tsum tau ua.

9. Thaum yuav tsum tau tswj impedance, txheej txheej tsis ua raws li qhov yuav tsum tau ua.

Six, power module requirements

1. Cov txheej txheem ntawm cov khoom siv hluav taws xob ua kom ntseeg tau tias cov kab tawm tswv yim thiab cov khoom siv tau zoo thiab tsis txhob hla.

2. Thaum lub rooj tsavxwm ib leeg muab lub zog rau lub subboard, tso cov lim dej sib txuas ze ze ntawm lub qhov hluav taws xob ntawm ib lub rooj tsavxwm thiab lub zog nkag ntawm lub subboard.

Xya, lwm yam kev xav tau

1. Lub layout yuav siv sij hawm mus rau hauv tus account tag nrho smoothness ntawm cov hlau, thiab cov ntaub ntawv tseem ceeb txaus yog tsim nyog.

2. Kho tus pin txoj hauj lwm ntawm kev cais tawm, FPGA, EPLD, tus tsav tsheb npav thiab lwm yam khoom siv raws li cov txiaj ntsig layout txhawm rau txhim kho qhov layout.

3. Cov txheej txheem yuav siv sij hawm rau hauv tus account qhov tsim nyog nce ntawm qhov chaw ntawm cov xov hlau ntom ntom kom tsis txhob muaj qhov xwm txheej uas nws tsis tuaj yeem hla.

4. Yog tias cov khoom siv tshwj xeeb, cov khoom siv tshwj xeeb (xws li 0.5mmBGA, thiab lwm yam), thiab cov txheej txheem tshwj xeeb tau txais, lub sijhawm xa khoom thiab kev ua haujlwm tau raug txiav txim siab tag nrho, thiab tau lees paub los ntawm PCB cov tuam txhab thiab cov neeg ua haujlwm txheej txheem.

5. Tus pin sib raug zoo ntawm gusset connector tau raug lees paub los tiv thaiv kev taw qhia thiab kev taw qhia ntawm gusset connector los ntawm kev thim rov qab.

6. If there are ICT test requirements, consider the feasibility of adding ICT test points during layout, so as to avoid difficulty in adding test points during the wiring phase.

7. When a high-speed optical module is included, the layout of the optical port transceiver circuit is prioritized.

8. Tom qab qhov kev teeb tsa tiav lawm, 1: 1 sib dhos kos duab tau muab rau cov neeg ua haujlwm los xyuas seb qhov kev xaiv pob khoom puas raug rau cov khoom siv.

9. Thaum qhib lub qhov rais, lub dav hlau sab hauv tau raug txiav txim siab tias yuav tsum tau thim rov qab, thiab ib qho kev txwv tsis pub siv hluav taws xob tsim nyog tau teeb tsa.