In design, layout is an important part. The quality of the layout result will directly affect the effect of the wiring, so it can be considered that a reasonable layout is the first step to a successful PCB design. Especially the pre-layout is the process of thinking about the entire circuit board, signal flow, heat dissipation, structure and other structures. If the pre-layout fails, no amount of effort will be needed.

PCB layout design The design process flow of printed circuit boards includes schematic design, electronic component database registration, design preparation, block division, electronic component configuration, configuration confirmation, wiring and final inspection. In the process of the process, no matter which process is found to be a problem, it must be returned to the previous process for reconfirmation or correction.

Hoʻopuka mua kēia ʻatikala i nā lula a me nā ʻenehana hoʻolālā PCB, a laila wehewehe i ke ʻano o ka hoʻolālā ʻana a me ka nānā ʻana i ka hoʻolālā PCB, mai nā koi DFM o ka hoʻolālā, nā koi hoʻolālā thermal, nā koi pono hōʻailona, ​​​​nā koi EMC, nā hoʻonohonoho papa a me nā koi ʻāina māhele mana, a mana modules. E nānā pono ʻia nā koi a me nā mea ʻē aʻe, a e hahai i ka mea hoʻoponopono e ʻike i nā kikoʻī.

Nā lula hoʻolālā hoʻolālā PCB

1. Ma lalo o nā kūlana maʻamau, pono e hoʻonohonoho ʻia nā ʻāpana āpau ma ka ʻili like o ka papa kaapuni. Aia wale nō ke ʻano o nā ʻāpana o ka pae kiʻekiʻe, hiki ke hoʻokomo ʻia kekahi mau mea me ke kiʻekiʻe liʻiliʻi a me ka hana wela haʻahaʻa, e like me nā pale pale chip, nā capacitors chip, a me nā capacitors chip. Hoʻokomo ʻia ʻo Chip IC, etc. ma ka papa haʻahaʻa.

2. Ma lalo o ka manaʻo o ka hōʻoia ʻana i ka hana uila, pono e kau ʻia nā ʻāpana ma ka pā a hoʻonohonoho like ʻole a kū pololei paha kekahi i kekahi i mea e maʻemaʻe a nani. Ma lalo o nā kūlana maʻamau, ʻaʻole ʻae ʻia nā ʻāpana e overlap; pono ka hoʻonohonoho ʻana o nā ʻāpana, a pono e hoʻonohonoho ʻia nā ʻāpana ma ka hoʻolālā holoʻokoʻa. ʻO ka māhele like ʻana a paʻa.

3. The minimum distance between adjacent land patterns of different components on the circuit board should be above 1mm.

4. ʻAʻole emi ka mamao mai ka lihi o ka papa kaapuni ma lalo o 2MM. ʻO ke ʻano maikaʻi loa o ka papa kaapuni he ʻāpana ʻehā, a ʻo ka lākiō hiʻohiʻona ʻo 3:2 a i ʻole 4:3. Ke ʻoi aku ka nui o ka papa kaapuni ma mua o 200MM a 150MM, e noʻonoʻo i ka mea hiki i ka papa kaapuni ke kū i ka ikaika Mechanical.

PCB layout design skills

I ka hoʻolālā hoʻolālā o ka PCB, pono e nānā ʻia nā ʻāpana o ka papa kaapuni, a pono e hoʻokumu ʻia ka hoʻolālā hoʻolālā ma ka hana hoʻomaka. I ka waiho ʻana i nā ʻāpana āpau o ke kaapuni, pono e hoʻokō ʻia nā loina:

1. E hoʻonohonoho i ke kūlana o kēlā me kēia hui kaapuni hana e like me ke kahe kaapuni, i maʻalahi ka hoʻolālā no ka neʻe ʻana o ka hōʻailona, ​​a mālama ʻia ka hōʻailona ma ka ʻaoʻao like me ka hiki [1].

2. Take the core components of each functional unit as the center and lay out around him. The components should be uniformly, integrally and compactly arranged on the PCB to minimize and shorten the leads and connections between the components.

3. No nā kaapuni e hana ana i nā alapine kiʻekiʻe, pono e noʻonoʻo ʻia nā ʻāpana mahele ma waena o nā ʻāpana. I nā kaapuni maʻamau, pono e hoʻonohonoho ʻia nā ʻāpana e like me ka mea hiki, ʻaʻole nani wale nō, akā maʻalahi hoʻi e hoʻokomo a maʻalahi hoʻi i nā huahana lehulehu.

Pehea e hoʻolālā a nānā i ka hoʻolālā PCB

1. DFM requirements for layout

1. Ua hoʻoholo ʻia ke ala kaʻina hana maikaʻi loa, a ua kau ʻia nā mea hana a pau ma ka papa.

2. The origin of the coordinates is the intersection of the left and lower extension lines of the board frame, or the lower left pad of the lower left socket.

3. The actual size of the PCB, the location of the positioning device, etc. are consistent with the process structure element map, and the device layout of the area with restricted device height requirements meets the requirements of the structure element map.

4. He kūpono ke kūlana o ka hoʻololi kelepona, ka mea hoʻoponopono hou, ke kukui hōʻailona, ​​a me nā mea ʻē aʻe, a ʻaʻole hoʻopilikia ka pahu lima i nā mea a puni.

5. ʻO ka papa waho o ka papa he 197mil maʻemaʻe, a i ʻole i hoʻolālā ʻia e like me ke kaha kiʻi nui.

6. He 200mil nā ʻaoʻao kaʻina hana nā papa maʻamau; ʻO ka ʻaoʻao hema a me ka ʻaoʻao ʻākau o ka mokulele hope he mau ʻaoʻao kaʻina hana ʻoi aku ka nui ma mua o 400mil, a ʻo nā ʻaoʻao luna a me lalo he mau ʻaoʻao kaʻina hana ʻoi aku ma mua o 680mil. ʻAʻole kūʻē ka hoʻokomo ʻana me ke kūlana wehe o ka puka makani.

7. All kinds of additional holes (ICT positioning hole 125mil, handle bar hole, elliptical hole and fiber holder hole) that need to be added are all missing and set correctly.

8. ʻO ka pitch pin pitch, ke kuhikuhi ʻana o ka mea hana, ka pitch device, ka hale waihona puke, a me nā mea ʻē aʻe i hana ʻia e ka nalu nalu e noʻonoʻo i nā koi o ke kūʻai ʻana.

9. The device layout spacing meets the assembly requirements: surface mount devices are greater than 20mil, IC is greater than 80mil, and BGA is greater than 200mil.

10. ʻO nā ʻāpana crimping i ʻoi aku ma mua o 120 mils i ka mamao o ka ʻili o ka ʻāpana, ʻaʻohe mea hana ma waena o nā ʻāpana crimping ma ka ili kuʻi.

11. ʻAʻohe mea pōkole ma waena o nā mea kiʻekiʻe, ʻaʻohe mea hoʻopili a me nā mea hoʻopili pōkole a me nā mea liʻiliʻi i hoʻokomo ʻia i loko o 5mm ma waena o nā mea me ke kiʻekiʻe ma mua o 10mm.

12. Loaʻa i nā mea polar nā polarity silkscreen logos. ʻO nā kuhikuhi X a me Y o ke ʻano like o nā mea hoʻopili polarized ua like.

13. All devices are clearly marked, no P*, REF, etc. are not clearly marked.

14. Aia he 3 mau kuhi hoʻonohonoho ma ka ʻili i loaʻa nā mea SMD, i hoʻokomo ʻia ma ke ʻano “L”. ʻOi aku ka mamao ma waena o ke kikowaena o ka piko hoʻonohonoho a me ka lihi o ka papa ma mua o 240 mils.

15. Inā pono ʻoe e hana i ka hoʻoili ʻana i ka papa, ua manaʻo ʻia ka hoʻolālā e hoʻomaʻamaʻa i ka hoʻokele a me ka PCB a me ka hui ʻana.

16. Pono e hoʻopiha ʻia nā ʻaoʻao i ʻoki ʻia (nā ʻaoʻao ʻē aʻe) ma o ka wili ʻana i nā ʻāpana a me nā lua peʻa. ʻO ka puka hōʻailona he mea ʻole i hoʻoheheʻe ʻia, ma ke ʻano he 40 mils ke anawaena a me 16 mils mai ka lihi.

17. The test points used for debugging have been added in the schematic diagram, and they are placed appropriately in the layout.

ʻO ka lua, nā koi hoʻolālā wela o ka hoʻolālā

1. Heating components and exposed components of the casing are not in close proximity to wires and heat-sensitive components, and other components should also be properly kept away.

2. The placement of the radiator takes into account the convection problem, and there is no interference of high components in the projection area of ​​the radiator, and the range is marked on the mounting surface with silk screen.

3. E noʻonoʻo ana ka hoʻolālā i nā ala hoʻoheheʻe wela kūpono.

4. Pono e hoʻokaʻawale ponoʻia ka capacitor electrolytic mai ka mea wela wela.

5. E noʻonoʻo i ka hoʻopau ʻana o ka wela o nā mea mana kiʻekiʻe a me nā mea hana ma lalo o ka gusset.

ʻO ke kolu, ʻo ka hōʻailona pono o ka hoʻolālā

1. The start-end matching is close to the sending device, and the end matching is close to the receiving device.

2. Place decoupling capacitors close to related devices

3. Place crystals, crystal oscillators and clock drive chips close to related devices.

4. Hoʻonohonoho kaʻawale ʻia ka wikiwiki kiʻekiʻe a me ka haʻahaʻa, digital a me analog e like me nā modula.

5. E hoʻoholo i ke ʻano topological o ke kaʻa e pili ana i ka loiloi a me nā hopena simulation a i ʻole ka ʻike i loaʻa e hōʻoia i ka hoʻokō ʻana i nā koi ʻōnaehana.

6. If it is to modify the board design, simulate the signal integrity problem reflected in the test report and give a solution.

7. The layout of the synchronous clock bus system meets the timing requirements.

ʻEhā, nā koi EMC

1. Inductive devices that are prone to magnetic field coupling, such as inductors, relays, and transformers, should not be placed close to each other. When there are multiple inductance coils, the direction is vertical and they are not coupled.

2. I mea e pale aku ai i ka hoʻopili electromagnetic ma waena o ka mea ma ka ili kuʻi ʻana o ka papa hoʻokahi a me ka papa hoʻokahi e pili ana, ʻaʻole pono e kau ʻia nā mea maʻalahi a me nā mea uila ikaika ma luna o ka ili kuʻi o ka papa hoʻokahi.

3. The interface components are placed close to the edge of the board, and appropriate EMC protection measures have been taken (such as shielding shells, hollowing out of the power supply ground, etc.) to improve the EMC capability of the design.

4. Hoʻonoho ʻia ke kaapuni pale ma kahi kokoke i ke kaapuni interface, ma muli o ke kumu o ka pale mua a laila kānana.

5. ʻO ka mamao mai ke kino pale a me ka puʻupuʻu pale i ke kino pale a me ka uhi uhi pale i ʻoi aku ma mua o 500 mils no nā mea hana me ka mana hoʻouna kiʻekiʻe a i ʻole ka maʻalahi (e like me nā oscillators crystal, crystals, etc.).

6. A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong devices and signals.

Five, layer setting and power supply and ground division requirements

1. Ke pili pono nā papa hōʻailona ʻelua i kekahi, pono e wehewehe ʻia nā lula uwila kū.

2. ʻO ka papa mana nui e pili ana i kona papa lepo e like me ka mea hiki, a hui ka mana mana i ka lula 20H.

3. Each wiring layer has a complete reference plane.

4. Ua laminated ʻia nā papa ʻāpana he nui a ua like ke ʻano kumu (CORE) i mea e pale ai i ka warping ma muli o ka hāʻawi like ʻole ʻana o ka ʻili keleawe a me ka mānoanoa asymmetrical o ka waena.

5. ʻAʻole pono ka mānoanoa o ka papa ma mua o 4.5mm. No ka poʻe me ka mānoanoa nui ma mua o 2.5mm (backplane ʻoi aku ka nui ma mua o 3mm), pono nā technicians i hōʻoia ʻaʻohe pilikia me ka PCB hana, hui, a me nā mea hana, a ʻo ka mānoanoa o ka papa kāleka PC he 1.6mm.

6. Ke oi aku ka mānoanoa-i-diameter ratio o ka via ma mua o 10:1, e hooiaio ia e ka mea hana PCB.

7. The power and ground of the optical module are separated from other power and ground to reduce interference.

8. Hoʻokō ka mana a me ka hana ʻāina o nā mea nui i nā koi.

9. Ke koi ‘ia ka mana impedance, e ho’okō ‘ia nā palena ho’onohonoho papa i nā koi.

Six, power module requirements

1. ʻO ka hoʻonohonoho ʻana o ka ʻāpana lako mana e hōʻoiaʻiʻo i ka maʻalahi o nā laina hoʻokomo a me nā laina hoʻopuka a ʻaʻole i keʻa.

2. Ke hāʻawi ka papa hoʻokahi i ka mana i ka subboard, e kau i ke kaapuni kānana pili kokoke i ka puka mana o ka papa hoʻokahi a me ka puka mana o ka subboard.

ʻEhiku, koi ʻē aʻe

1. Ka hoʻolālā e noʻonoʻo i ka laumania holoʻokoʻa o ka uea, a kūpono ke kahe ʻikepili nui.

2. E hoʻoponopono i nā hana pine o ka hoʻokuʻu ʻia, FPGA, EPLD, kaʻa kaʻa a me nā mea hana ʻē aʻe e like me nā hopena hoʻonohonoho e hoʻonui i ka hoʻolālā.

3. E noʻonoʻo ana ka hoʻolālā i ka hoʻonui kūpono o ka hakahaka ma nā uwea paʻa e pale aku i ke kūlana ʻaʻole hiki ke holo.

4. Inā hoʻohanaʻia nā mea kūikawā, nā mea hana kūikawā (e like me 0.5mmBGA, a me nā mea’ē aʻe), a me nā kaʻina hana kūikawā, ua noʻonoʻo ponoʻia ka manawa hoʻouna a me ka hana, a ua hōʻoiaʻiʻoʻia e nā mea hana PCB a me nā limahana hana.

5. Ua hōʻoia ʻia ka pilina pili o ka mea hoʻopili gusset i mea e pale ai i ka hoʻohuli ʻana i ke kuhikuhi a me ka hoʻonohonoho ʻana o ka mea hoʻohui gusset.

6. If there are ICT test requirements, consider the feasibility of adding ICT test points during layout, so as to avoid difficulty in adding test points during the wiring phase.

7. When a high-speed optical module is included, the layout of the optical port transceiver circuit is prioritized.

8. Ma hope o ka pau ʻana o ka hoʻonohonoho ʻana, ua hāʻawi ʻia kahi kiʻi hui 1: 1 no ka poʻe limahana o ka papahana e nānā inā pololei ke koho ʻana i ka pūʻolo hāmeʻa i ka hui.

9. I ka wehe ʻana o ka puka makani, ua manaʻo ʻia e hoʻihoʻi ʻia ka mokulele i loko, a ua hoʻonohonoho ʻia kahi wahi pāpā uea kūpono.