Through the analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. E ho’āʻo ʻaʻole e hoʻololi i nā papa o nā hōʻailona hōʻailona ma ka papa PCB, ʻo ia hoʻi, e hoʻāʻo e hoʻohana i nā vias pono ʻole.

4. Pono e wili ʻia ka mana a me ka lepo ma kahi kokoke, a ʻo ke alakaʻi ma waena o ka via a me ka pine e like me ka pōkole, no ka mea e hoʻonui lākou i ka inductance. I ka manawa like, pono e mānoanoa ka mana a me nā alakaʻi honua e hōʻemi i ka impedance.

5. E kau i kekahi mau vias i hoʻopaʻa ʻia ma kahi kokoke i nā vias o ka papa hōʻailona e hāʻawi i ka loop loop kokoke loa no ka hōʻailona. Hiki paha ke kau i kahi helu nui o ka ʻāina ma luna o ka papa PCB. ʻOiaʻiʻo, pono e maʻalahi ka hoʻolālā. ʻO ke kumu hoʻohālike i kūkākūkā ʻia ma mua, ʻo ia ka hihia i loaʻa nā pads ma kēlā me kēia papa. I kekahi manawa, hiki iā mākou ke hōʻemi a wehe paha i nā pad o kekahi mau papa. ʻOi loa ke kiʻekiʻe loa o ka mānoanoa o nā vias, hiki ke alakaʻi i ke kūkulu ʻana i kahi awāwa haʻihaʻi e hoʻokaʻawale i ka loop i ka papa keleawe. No ka hoʻoponopono ʻana i kēia pilikia, ma waho aʻe o ka hoʻoneʻe ʻana i ke kūlana o ka via, hiki iā mākou ke noʻonoʻo e kau i ka via ma ka papa keleawe. Hoʻemi ʻia ka nui o ka pā.