In design, layout is an important part. The quality of the layout result will directly affect the effect of the wiring, so it can be considered that a reasonable layout is the first step to a successful PCB design. Especially the pre-layout is the process of thinking about the entire circuit board, signal flow, heat dissipation, structure and other structures. If the pre-layout fails, no amount of effort will be needed.

PCB layout design The design process flow of printed circuit boards includes schematic design, electronic component database registration, design preparation, block division, electronic component configuration, configuration confirmation, wiring and final inspection. In the process of the process, no matter which process is found to be a problem, it must be returned to the previous process for reconfirmation or correction.

Isiokwu a na-ebu ụzọ ewebata iwu na usoro nhazi nhazi PCB, wee kọwaa otú e si emepụta na nyochaa nhazi PCB, site na nhazi DFM chọrọ, ihe ndị chọrọ imewe okpomọkụ, ihe mgbaàmà nke iguzosi ike n’ezi ihe, ihe EMC chọrọ, ntọala oyi akwa na nkewa ike ala chọrọ, na modul ike. A ga-enyocha ihe ndị a chọrọ na akụkụ ndị ọzọ nke ọma, ma soro onye nchịkọta akụkọ ka ịchọta nkọwa.

PCB okirikiri nhọrọ ukwuu iwu imewe

1. N’okpuru ọnọdụ nkịtị, a ga-edozi ihe niile dị n’otu elu nke bọọdụ sekit. Naanị mgbe ihe ndị dị n’elu-larịị dị oke oke, enwere ike itinye ụfọdụ ngwaọrụ ndị nwere oke ịdị elu na obere okpomọkụ, dị ka mgbawa mgbawa, mgbawa capacitors na mgbawa capacitors. A na-etinye Chip IC, wdg na oyi akwa ala.

2. N’okpuru ebe a na-ahụ maka ịrụ ọrụ eletriki, a ga-etinye ihe ndị ahụ na grid ma hazie ya n’otu n’otu ma ọ bụ perpendicular na ibe ya ka ọ dị mma ma mara mma. N’okpuru ọnọdụ nkịtị, a naghị ekwe ka ihe ndị ahụ gbasaa; nhazi nke ihe ndị ahụ kwesịrị ịbụ kọmpat, na ihe ndị ahụ kwesịrị ịhazi na nhazi dum. Nkesa bụ otu na oke.

3. The minimum distance between adjacent land patterns of different components on the circuit board should be above 1mm.

4. Ebe dị anya site na nsọtụ osisi sekit na-abụkarị ọ bụghị ihe na-erughị 2MM. Ụdị kachasị mma nke bọọdụ sekit bụ akụkụ anọ, akụkụ akụkụ ya bụ 3: 2 ma ọ bụ 4: 3. Mgbe nha nke bọọdụ sekit karịrị 200MM site na 150MM, tụlee ihe bọọdụ sekit nwere ike iguzogide ike Mechanical.

PCB layout design skills

Na nhazi nhazi nke PCB, a ga-enyocha nkeji nke bọọdụ sekit, na nhazi nhazi kwesịrị ịdabere na ọrụ mmalite. Mgbe ị na-edobe akụkụ niile nke sekit, ụkpụrụ ndị a kwesịrị imezu:

1. Hazie ọnọdụ nke sekit ọ bụla na-arụ ọrụ dị ka mgbagharị sekit si dị, ka nhazi ahụ wee dị mma maka mgbasa ozi, ma debe akara ngosi ahụ n’otu ụzọ ahụ dịka o kwere mee [1].

2. Take the core components of each functional unit as the center and lay out around him. The components should be uniformly, integrally and compactly arranged on the PCB to minimize and shorten the leads and connections between the components.

3. Maka sekit na-arụ ọrụ n’ogo dị elu, a ghaghị ịtụle nkesa nkesa n’etiti ihe ndị dị na ya. Na sekit n’ozuzu, a ghaghị ịhazi ihe ndị dị na ya dị ka o kwere mee, nke na-abụghị nanị mara mma, kamakwa ọ dị mfe ịwụnye ma dị mfe ịmepụta ọtụtụ ihe.

Otu esi emepụta na nyochaa nhazi PCB

1. DFM requirements for layout

1. Achọpụtala ụzọ usoro kachasị mma, ma tinyekwa ngwaọrụ niile na osisi.

2. The origin of the coordinates is the intersection of the left and lower extension lines of the board frame, or the lower left pad of the lower left socket.

3. The actual size of the PCB, the location of the positioning device, etc. are consistent with the process structure element map, and the device layout of the area with restricted device height requirements meets the requirements of the structure element map.

4. Ọnọdụ nke ngbanwe ọkpụkpọ, ngwaọrụ nrụpụta, ọkụ na-egosi, wdg kwesịrị ekwesị, na ogwe aka adịghị egbochi ngwaọrụ ndị gbara ya gburugburu.

5. Oghere dị n’elu nke osisi ahụ nwere radian dị nro nke 197mil, ma ọ bụ e mere ya dị ka eserese nhazi nhazi.

6. mbadamba nkịtị nwere akụkụ usoro 200mil; n’akụkụ aka ekpe na aka nri nke backplane nwere usoro n’ọnụ karịa 400mil, na elu na ala n’akụkụ nwere usoro n’ọnụ ka 680mil. Ntinye ngwaọrụ anaghị emegide ọnọdụ oghere windo.

7. All kinds of additional holes (ICT positioning hole 125mil, handle bar hole, elliptical hole and fiber holder hole) that need to be added are all missing and set correctly.

8. Ngwa pin pitch, ntụziaka ngwaọrụ, ngwaọrụ pitch, ngwaọrụ n’ọbá akwụkwọ, wdg na-esikwa na-efegharị soldering na-eburu n’uche chọrọ nke ife soldering.

9. The device layout spacing meets the assembly requirements: surface mount devices are greater than 20mil, IC is greater than 80mil, and BGA is greater than 200mil.

10. The crimping akụkụ nwere ihe karịrị 120 mils na akụrụngwa elu anya, na ọ dịghị ngwaọrụ na site na ebe nke crimping akụkụ na ịgbado ọkụ n’elu.

11. Enweghị ngwaọrụ dị mkpirikpi n’etiti ngwaọrụ ogologo, ọ dịghịkwa ngwaọrụ patch na obere na obere interposing ngwaọrụ na-etinye n’ime 5mm n’etiti ngwaọrụ nwere elu karịa 10mm.

12. Polar ngwaọrụ nwere polarity silkscreen logos. Ntụziaka X na Y nke otu ụdị ngwa mgbakwunye pọlarịịd bụ otu.

13. All devices are clearly marked, no P*, REF, etc. are not clearly marked.

14. Enwere 3 cursors n’elu nke nwere ngwaọrụ SMD, nke etinyere n’ụdị “L”. Ebe dị n’etiti etiti cursor n’ọnọdu na nsọtụ osisi karịrị 240 mils.

15. Ọ bụrụ na ịchọrọ ịme nhazi nhazi, a na-atụle nhazi ahụ iji kwado nhazi na PCB nhazi na mgbakọ.

16. Ekwesịrị ka ejupụta akụkụ ndị ahụ gbawara agbawa (akụkụ ndị na-adịghị mma) site na igwe igwe igwe na oghere stampụ. Oghere stampụ bụ ihe efu na-abụghị metallized, n’ozuzu 40 mils na dayameta yana 16 mils site na nsọtụ.

17. The test points used for debugging have been added in the schematic diagram, and they are placed appropriately in the layout.

Second, the thermal design requirements of the layout

1. Heating components and exposed components of the casing are not in close proximity to wires and heat-sensitive components, and other components should also be properly kept away.

2. The placement of the radiator takes into account the convection problem, and there is no interference of high components in the projection area of ​​the radiator, and the range is marked on the mounting surface with silk screen.

3. Nhazi ahụ na-eburu n’uche na ọwa ikposa ọkụ dị mma ma dị mma.

4. The electrolytic capacitor kwesịrị ikewapụ nke ọma na ngwaọrụ dị elu.

5. Tụlee ikpochapụ okpomọkụ nke ngwaọrụ na ngwaọrụ dị elu n’okpuru gusset.

Nke atọ, akara ngosi iguzosi ike n’ezi ihe chọrọ nke nhazi

1. The start-end matching is close to the sending device, and the end matching is close to the receiving device.

2. Place decoupling capacitors close to related devices

3. Place crystals, crystal oscillators and clock drive chips close to related devices.

4. A na-ahazi ngwa ngwa dị elu na nke dị ala, dijitalụ na analog dị iche iche dịka modul.

5. Determine the topological structure of the bus based on the analysis and simulation results or the existing experience to ensure that the system requirements are met.

6. If it is to modify the board design, simulate the signal integrity problem reflected in the test report and give a solution.

7. The layout of the synchronous clock bus system meets the timing requirements.

Anọ, EMC chọrọ

1. Inductive devices that are prone to magnetic field coupling, such as inductors, relays, and transformers, should not be placed close to each other. When there are multiple inductance coils, the direction is vertical and they are not coupled.

2. Iji zere nnyonye anya electromagnetic n’etiti ngwaọrụ n’elu ịgbado ọkụ nke otu osisi na otu osisi dị n’akụkụ, ọ dịghị ngwaọrụ ndị nwere mmetụta siri ike na ngwaọrụ radieshon siri ike kwesịrị itinye n’elu ebe ịgbado ọkụ nke otu osisi.

3. The interface components are placed close to the edge of the board, and appropriate EMC protection measures have been taken (such as shielding shells, hollowing out of the power supply ground, etc.) to improve the EMC capability of the design.

4. A na-etinye sekit nchebe nso nso sekit interface, na-agbaso ụkpụrụ nke nchebe mbụ na mgbe ahụ nzacha.

5. Ebe dị anya site na ihe mkpuchi ahụ na mkpuchi mkpuchi na mkpuchi mkpuchi na mkpuchi mkpuchi bụ ihe karịrị 500 mils maka ngwaọrụ ndị nwere ike na-ebufe elu ma ọ bụ karịsịa mmetụta (dị ka oscillators kristal, kristal, wdg).

6. A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong devices and signals.

Five, layer setting and power supply and ground division requirements

1. Mgbe okpukpu abụọ mgbaàmà dị n’akụkụ ibe ha, a ghaghị ịkọwa iwu wiring vetikal.

2. Isi oyi akwa dị n’akụkụ ya kwekọrọ na oyi akwa ala dị ka o kwere mee, na oyi akwa na-ezute iwu 20H.

3. Each wiring layer has a complete reference plane.

4. Multi-oyi akwa mbadamba na-laminated na isi ihe (isi) bụ symmetrical iji gbochie warping mere na-ezighị ezi nkesa ọla kọpa akpụkpọ njupụta na asymmetrical ọkpụrụkpụ nke ọkara.

5. Ọkpụrụkpụ nke osisi ekwesịghị gafere 4.5mm. Maka ndị nwere ọkpụrụkpụ karịa 2.5mm (azụ ụgbọ elu karịa 3mm), ndị ọrụ nka kwesịrị ekwenye na enweghị nsogbu na nhazi, mgbakọ na ngwa PCB, na ọkpụrụkpụ kaadị PC bụ 1.6mm.

6. Mgbe ọkpụrụkpụ-na-dayameta ruru nke via bụ ukwuu karịa 10: 1, ọ ga-kwetara site PCB emeputa.

7. The power and ground of the optical module are separated from other power and ground to reduce interference.

8. Ike na nhazi ala nke ihe ndị dị mkpa na-emezu ihe ndị a chọrọ.

9. Mgbe achọrọ njikwa impedance, paramita ntọala oyi akwa na-ezute ihe achọrọ.

Six, power module requirements

1. The layout of the power supply part ensures that the input and output lines are smooth and do not cross.

2. Mgbe otu bọọdụ ahụ na-enye ike na subboard, tinye sekit nzacha kwekọrọ na nso ọkụ nke otu bọọdụ na ntinye ike nke subboard.

Seven, other requirements

1. The layout takes into account the overall smoothness of the wiring, and the main data flow is reasonable.

2. Gbanwee pin ọrụ nke mwepu, FPGA, EPLD, ụgbọ ala ụgbọ ala na ngwaọrụ ndị ọzọ dị ka okirikiri nhọrọ ukwuu na-ebuli okirikiri nhọrọ ukwuu.

3. Nhazi ahụ na-eburu n’uche mmụba kwesịrị ekwesị nke oghere dị na wiwi dị ukwuu iji zere ọnọdụ na-enweghị ike ịmegharị ya.

4. Ọ bụrụ na ihe pụrụ iche, ngwaọrụ pụrụ iche (dị ka 0.5mmBGA, wdg), na usoro pụrụ iche na-anakwere, a na-atụle oge nnyefe na nhazi nke ọma, ma kwadoro ndị na-emepụta PCB na ndị ọrụ nhazi.

5. A kwadoro njikọ njikọ pin nke njikọ gusset iji gbochie ntụzịaka na ntụgharị nke njikọ gusset ka ọ gbanwee.

6. If there are ICT test requirements, consider the feasibility of adding ICT test points during layout, so as to avoid difficulty in adding test points during the wiring phase.

7. When a high-speed optical module is included, the layout of the optical port transceiver circuit is prioritized.

8. Mgbe emechara nhazi ahụ, a na-enye ihe osise 1: 1 maka ndị ọrụ na-arụ ọrụ iji chọpụta ma nhọrọ ngwugwu ngwaọrụ ahụ ziri ezi megide ụlọ ọrụ ngwaọrụ.

9. N’elu oghere nke windo, a na-ewere ụgbọ elu dị n’ime ka ọ ga-eweghachite, ma debe ebe mmachibido iwu wiring kwesịrị ekwesị.