Through the analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. Gbalịa ka ị ghara ịgbanwe n’ígwé nke mgbaàmà traces na PCB osisi, ya bụ, gbalịa ka ị ghara iji na-enweghị isi vias.

4. Ekwesịrị ịkụnye ike na ntụtụ ala dị nso, na ụzọ dị n’etiti via na ntụtụ kwesịrị ịdị mkpụmkpụ dị ka o kwere mee, n’ihi na ha ga-amụba inductance. N’otu oge ahụ, ike na ala na-eduga kwesịrị ịdị oke dị ka o kwere mee iji belata mgbochi.

5. Tinye ụfọdụ vias ala n’akụkụ vias nke oyi akwa mgbama iji nye akara kacha nso maka mgbama. Ọ ga-ekwe omume itinye ọnụ ọgụgụ buru ibu nke ala na-adịghị arụ ọrụ na bọọdụ PCB. N’ezie, imewe kwesịrị ịdị na-agbanwe agbanwe. Ihe nlereanya a tụlere na mbụ bụ ikpe ebe e nwere pad na oyi akwa ọ bụla. Mgbe ụfọdụ, anyị nwere ike ibelata ma ọ bụ ọbụna wepụ pads nke ụfọdụ n’ígwé. Karịsịa mgbe njupụta nke vias dị oke elu, ọ nwere ike iduga n’ịmepụta oghere nkwụsịtụ nke na-ekewa akaghị na oyi akwa ọla kọpa. Iji dozie nsogbu a, na mgbakwunye na ịkwaga ọnọdụ nke via, anyị nwekwara ike ịtụle itinye via na oyi akwa ọla kọpa. A na-ebelata nha mpe mpe akwa.