Through the analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. Coba ora kanggo ngganti lapisan saka ngambah sinyal ing Papan PCB, sing ngomong, nyoba ora nggunakake vias rasah.

4. Daya lan lemah lencana kudu dilatih cedhak, lan timbal antarane liwat lan pin kudu cendhak sabisa, amarga padha bakal nambah induktansi. Ing wektu sing padha, daya lan timbal lemah kudu dadi kandel kanggo nyuda impedansi.

5. Selehake sawetara vias grounded cedhak vias saka lapisan sinyal kanggo nyedhiyani daur ulang paling cedhak kanggo sinyal. Sampeyan malah bisa kanggo nyeleh nomer akeh vias lemah keluwih ing Papan PCB. Mesthine, desain kudu fleksibel. Model liwat sing dibahas sadurunge yaiku kasus sing ana bantalan ing saben lapisan. Kadhangkala, kita bisa nyuda utawa malah mbusak bantalan sawetara lapisan. Utamané nalika Kapadhetan saka vias dhuwur banget, bisa mimpin kanggo tatanan saka break alur sing misahake daur ulang ing lapisan tembaga. Kanggo ngatasi masalah iki, saliyane kanggo mindhah posisi liwat, kita uga bisa nimbang manggonke liwat ing lapisan tembaga. Ukuran pad dikurangi.