In design, layout is an important part. The quality of the layout result will directly affect the effect of the wiring, so it can be considered that a reasonable layout is the first step to a successful PCB design. Especially the pre-layout is the process of thinking about the entire circuit board, signal flow, heat dissipation, structure and other structures. If the pre-layout fails, no amount of effort will be needed.

PCB layout design The design process flow of printed circuit boards includes schematic design, electronic component database registration, design preparation, block division, electronic component configuration, configuration confirmation, wiring and final inspection. In the process of the process, no matter which process is found to be a problem, it must be returned to the previous process for reconfirmation or correction.

Ko tenei tuhinga ka whakaatu tuatahi i nga ture hoahoa tahora PCB me nga tikanga, ka whakamarama me pehea te hoahoa me te tirotiro i te whakatakotoranga PCB, mai i nga whakaritenga DFM o te whakatakotoranga, nga whakaritenga hoahoa waiariki, nga whakaritenga tapatahi tohu, nga whakaritenga EMC, nga tautuhinga paparanga me nga whakaritenga wehenga whenua mana, me kōwae hiko. Ko nga whakaritenga me etahi atu waahanga ka tino wetewetehia, ka whai i te kaiwhakatika kia kitea nga korero.

ture hoahoa tahora PCB

1. I raro i nga ahuatanga noa, me whakarite nga waahanga katoa ki runga i te mata kotahi o te poari ara iahiko. Anake ina he mato rawa nga waahanga o runga, ka taea e etahi taputapu iti te teitei me te iti o te whakangao wera, penei i nga parenga maramara, nga punga maramara, me nga punga maramara, te whakauru. Ko te maramara IC, me etahi atu ka whakanohoia ki runga i te paparanga o raro.

2. I raro i te kaupapa o te whakarite i nga mahi hiko, me whakanoho nga waahanga ki runga i te matiti me te whakarite whakarara, kia noho tika ranei tetahi ki tetahi kia pai ai, kia ataahua. I raro i nga ahuatanga noa, kaore e whakaaetia nga waahanga ki te inaki; ko te whakatakotoranga o nga waahanga kia rite, me whakarite nga waahanga ki runga i te whakatakotoranga katoa. He rite te tohatoha me te matotoru.

3. The minimum distance between adjacent land patterns of different components on the circuit board should be above 1mm.

4. Ko te tawhiti mai i te tapa o te poari ara iahiko ko te tikanga kaua e iti iho i te 2MM. Ko te ahua pai o te papa taiawhio he tapawhā, a ko te 3:2, 4:3 ranei te ahua ōwehenga. Ina nui ake te rahi o te poari ara iahiko i te 200MM ki te 150MM, whakaarohia he aha te kaha o te poari ara iahiko ki te kaha Miihini.

PCB layout design skills

I roto i te hoahoa tahora o te PCB, kia tātarihia nga waeine o te poari ara iahiko, a kia hāngai te hoahoa tahora i runga i te mahi tīmata. A, no te whakatakoto i nga waahanga katoa o te ara iahiko, me tutuki nga tikanga e whai ake nei:

1. Whakaritea te tuunga o ia waahanga iahiko mahi kia rite ki te rere o te ara iahiko, kia pai ai te whakatakotoranga mo te tohanga tohu, ka mau tonu te tohu ki te huarahi kotahi ka taea [1].

2. Take the core components of each functional unit as the center and lay out around him. The components should be uniformly, integrally and compactly arranged on the PCB to minimize and shorten the leads and connections between the components.

3. Mo nga iahiko e mahi ana i nga iarere teitei, me whakaaro nga tawhā tohatoha i waenga i nga waahanga. I roto i nga iahiko whanui, me whakarite nga waahanga kia rite ki te mea ka taea, ehara i te mea ataahua anake, engari he ngawari ki te whakauru me te ngawari ki te whakaputa papatipu.

Me pehea te hoahoa me te tirotiro i te whakatakotoranga PCB

1. DFM requirements for layout

1. Ko te huarahi tino pai kua whakatauhia, kua oti nga taputapu katoa ki runga i te papa.

2. The origin of the coordinates is the intersection of the left and lower extension lines of the board frame, or the lower left pad of the lower left socket.

3. The actual size of the PCB, the location of the positioning device, etc. are consistent with the process structure element map, and the device layout of the area with restricted device height requirements meets the requirements of the structure element map.

4. Ko te waahi o te waea waea, te taputapu tautuhi, te rama tohu, me etahi atu e tika ana, a kaore te kakau kakau e pokanoa ki nga taputapu a tawhio noa.

5. Ko te anga o waho o te poari he radian maeneene o 197mil, kua hangaia ranei kia rite ki te tuhi rahi o te hanganga.

6. Ko nga papa noa he 200mil nga taha tukanga; Ko nga taha maui me te taha matau o te waka rererangi he nui ake i te 400mil nga tapa, ko nga taha o runga me o raro he waahanga mahi nui ake i te 680mil. Ko te whakatakotoranga taputapu karekau e taupatupatu ki te turanga tuwhera matapihi.

7. All kinds of additional holes (ICT positioning hole 125mil, handle bar hole, elliptical hole and fiber holder hole) that need to be added are all missing and set correctly.

8. Ko te titi o te taputapu, te ahunga o te taputapu, te tima taputapu, te whare pukapuka taputapu, me etahi atu kua mahia e te ngaru ngaru ka whai whakaaro ki nga whakaritenga o te whakapiri ngaru.

9. The device layout spacing meets the assembly requirements: surface mount devices are greater than 20mil, IC is greater than 80mil, and BGA is greater than 200mil.

10. Neke atu i te 120 mils nga waahanga crimping i te tawhiti o te mata o te waahanga, a kaore he taputapu kei roto i te waahi o nga waahanga crimping i runga i te mata o te raima.

11. Karekau he taputapu poto i waenga i nga taputapu roroa, karekau he taputapu papaki me nga taputapu wawao poto me te iti ki roto i te 5mm i waenga i nga taputapu he teitei ake i te 10mm.

12. Ko nga taputapu polar he tohu polarity silkscreen. Ko nga ahunga X me te Y o te ahua o nga waahanga mono-polarized he rite tonu.

13. All devices are clearly marked, no P*, REF, etc. are not clearly marked.

14. E 3 nga pehu tuunga i runga i te mata kei roto nga taputapu SMD, ka whakanohohia ki te ahua “L”. Ko te tawhiti i waenganui i te pokapū o te pehu tuunga me te taha o te papa he nui ake i te 240 mils.

15. Mena ka hiahia koe ki te mahi i te tukatuka poari, ka whakaarohia te whakatakotoranga hei whakahaere i te poari me te tukatuka PCB me te huihuinga.

16. Ko nga tapa maramara (te taha kee) me whakakii ma te mira mira me nga kohao kuini. Ko te kohao pane kuini he kore-mehameha kore, ko te tikanga 40 mil te whanui me te 16 mil mai i te taha.

17. The test points used for debugging have been added in the schematic diagram, and they are placed appropriately in the layout.

Tuarua, ko nga whakaritenga hoahoa waiariki o te whakatakotoranga

1. Heating components and exposed components of the casing are not in close proximity to wires and heat-sensitive components, and other components should also be properly kept away.

2. The placement of the radiator takes into account the convection problem, and there is no interference of high components in the projection area of ​​the radiator, and the range is marked on the mounting surface with silk screen.

3. Ka whai whakaaro te whakatakotoranga ki nga waahana tohanga wera pai me te maeneene.

4. Me tika te wehe i te hiko hiko mai i te taputapu wera nui.

5. Whakaarohia te wera o te wera o nga taputapu hiko me nga taputapu i raro i te pupuhi.

Tuatoru, ko nga whakaritenga tapatahi tohu o te whakatakotoranga

1. The start-end matching is close to the sending device, and the end matching is close to the receiving device.

2. Place decoupling capacitors close to related devices

3. Place crystals, crystal oscillators and clock drive chips close to related devices.

4. Ko te tere-tere me te iti-tere, te matihiko me te tairitenga kua whakaritea motuhake kia rite ki nga waahanga.

5. Te whakatau i te hanganga topological o te pahi i runga i te tātaritanga me nga hua whaihanga, te wheako o naianei ranei hei whakarite kia tutuki nga whakaritenga o te punaha.

6. If it is to modify the board design, simulate the signal integrity problem reflected in the test report and give a solution.

7. The layout of the synchronous clock bus system meets the timing requirements.

E wha, nga whakaritenga EMC

1. Inductive devices that are prone to magnetic field coupling, such as inductors, relays, and transformers, should not be placed close to each other. When there are multiple inductance coils, the direction is vertical and they are not coupled.

2. Kia kore ai e pokanoa te hikohiko i waenga i te taputapu i runga i te mata whakapiri o te papa kotahi me te papa kotahi e tata ana, kaua nga taputapu tairongo me nga taputapu radiation kaha e tuu ki runga i te mata o te papa kotahi.

3. The interface components are placed close to the edge of the board, and appropriate EMC protection measures have been taken (such as shielding shells, hollowing out of the power supply ground, etc.) to improve the EMC capability of the design.

4. Ka whakanohoia te ara iahiko tiaki ki te taha o te ara iahiko atanga, e whai ana i te kaupapa o te whakamarumaru tuatahi katahi ka tātari.

5. Ko te tawhiti mai i te tinana whakamarumaru me te anga whakamarumaru ki te tinana whakamarumaru me te anga whakamarumaru whakamarumaru he nui atu i te 500 mils mo nga taputapu me te kaha whakawhiti teitei, tino tairongo ranei (penei i nga oscillators tioata, tioata, me etahi atu).

6. A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong devices and signals.

Five, layer setting and power supply and ground division requirements

1. Ina tata e rua nga papa tohu tohu ki a ratau, me tautuhi nga ture waea poutū.

2. Ko te paparanga mana matua e tata ana ki tana paparanga whenua e rite ana ki te mea ka taea, ka tutuki te paparanga mana ki te ture 20H.

3. Each wiring layer has a complete reference plane.

4. Kua whakakikoruatia nga papa paparanga maha, he hangarite te rauemi matua (CORE) kia kore ai e pakaru mai i te tohatoha koretake o te kiato kiri parahi me te matotoru hangarite o te reo.

5. Ko te matotoru o te papa kaua e neke ake i te 4.5mm. Mo te hunga he nui ake te matotoru i te 2.5mm (he nui ake te papamuri i te 3mm), me kii nga kaitoi kaore he raruraru mo te tukatuka PCB, te huihuinga, me nga taputapu, me te 1.6mm te matotoru o te poari kaari PC.

6. A, no te nui atu i te 10:1 te matotoru-ki-diameter ōwehenga o te via, ka whakapumautia e te kaihanga PCB.

7. The power and ground of the optical module are separated from other power and ground to reduce interference.

8. Ko te kaha me te tukatuka whenua o nga waahanga matua ka tutuki nga whakaritenga.

9. I te wa e hiahiatia ana te whakahaere impedance, ka tutuki nga tawhā tautuhinga paparanga ki nga whakaritenga.

Six, power module requirements

1. The layout of the power supply part ensures that the input and output lines are smooth and do not cross.

2. Ina tukuna e te papa kotahi te hiko ki te papa iti, tuuhia te ara iahiko tātari e rite ana ki te taha o te putanga hiko o te papa kotahi me te kokoru hiko o te papa iti.

E whitu, etahi atu whakaritenga

1. Ka whai whakaaro te whakatakotoranga ki te maeneene katoa o te waea waea, a he tika te rere o nga raraunga matua.

2. Whakaritea nga mahi titi o te whakakore, FPGA, EPLD, taraiwa pahi me etahi atu taputapu kia rite ki nga hua tahora ki te arotau i te whakatakotoranga.

3. Ka whai whakaaro te whakatakotoranga ki te pikinga tika o te mokowā ki te waea mātotoru kia kore ai e taea te haere.

4. Mena ka tangohia nga rauemi motuhake, nga taputapu motuhake (penei i te 0.5mmBGA, me etahi atu), me nga tukanga motuhake, kua tino whakaarohia te wa tuku me te mahinga, ka whakapumautia e nga kaihanga PCB me nga kaimahi tukatuka.

5. Ko te hononga titi o te hononga gusset kua whakapumautia kia kore ai e huri te ahunga me te takotoranga o te hononga gusset.

6. If there are ICT test requirements, consider the feasibility of adding ICT test points during layout, so as to avoid difficulty in adding test points during the wiring phase.

7. When a high-speed optical module is included, the layout of the optical port transceiver circuit is prioritized.

8. I muri i te otinga o te whakatakotoranga, kua tukuna he tuhi huinga 1:1 mo nga kaimahi o te kaupapa ki te tirotiro mena kei te tika te kowhiringa kete taputapu ki te hinonga taputapu.

9. I te whakatuwheratanga o te matapihi, kua kiia te waka rererangi o roto kua hoki mai, kua whakaritea he waahi aukati waea pai.