In design, layout is an important part. The quality of the layout result will directly affect the effect of the wiring, so it can be considered that a reasonable layout is the first step to a successful PCB design. Especially the pre-layout is the process of thinking about the entire circuit board, signal flow, heat dissipation, structure and other structures. If the pre-layout fails, no amount of effort will be needed.

PCB layout design The design process flow of printed circuit boards includes schematic design, electronic component database registration, design preparation, block division, electronic component configuration, configuration confirmation, wiring and final inspection. In the process of the process, no matter which process is found to be a problem, it must be returned to the previous process for reconfirmation or correction.

Ichi chinyorwa chinotanga kusuma PCB dhizaini dhizaini mitemo uye hunyanzvi, uyezve inotsanangura magadzirirwo nekuongorora magadzirirwo ePCB, kubva padhizaini yeDFM zvinodiwa, dhizaini yedhizaini zvinodiwa, chiratidzo chekuvimbika zvinodiwa, zvinodiwa zveEMC, zvigadziriso zvemutsetse uye simba rekupatsanura pasi zvinodiwa, uye simba modules. Zvinodiwa uye zvimwe zvinhu zvichaongororwa zvakadzama, uye tevera mupepeti kuti uwane ruzivo.

PCB dhizaini dhizaini mitemo

1. Mumamiriro ezvinhu akajairika, zvikamu zvose zvinofanira kurongwa panzvimbo imwechete yebhodhi redunhu. Chete kana zvikamu zvepamusoro-soro zvanyanya kuomarara, ndipo panogona kuiswa mimwe michina ine hurefu hushoma uye yakaderera kupisa, senge chip resistors, chip capacitor, uye chip capacitor, inogona kuiswa. Chip IC, nezvimwewo zvinoiswa pazasi.

2. Pasi pechikonzero chekuvimbisa kushanda kwemagetsi, zvikamu zvinofanira kuiswa pane gridhi uye zvakarongeka zvakafanana kana kuti perpendicular kune imwe neimwe kuitira kuti zvive zvakanaka uye zvakanaka. Mumamiriro ezvinhu akajairika, zvikamu hazvibvumirwi kupindirana; kurongeka kwezvikamu kunofanira kunge kwakabatana, uye zvikamu zvinofanira kurongeka pakugadzirisa kwose. Kugoverwa kwakafanana uye kwakaoma.

3. The minimum distance between adjacent land patterns of different components on the circuit board should be above 1mm.

4. Nharaunda kubva kumucheto kwebhodhi redunhu kazhinji haisi pasi pe2MM. Chimiro chakanakisa chebhodhi redunhu chine rectangular, uye chikamu chiyero ndeye 3: 2 kana 4: 3. Kana saizi yebhodhi redunhu yakakura kupfuura 200MM ne150MM, funga izvo bhodhi redunhu rinogona kumira Mechanical simba.

PCB layout design skills

Muchigadziro chekugadzirisa kwePCB, zvikamu zvebhodhi redunhu rinofanira kuongororwa, uye dhizaini yekugadzira inofanira kunge yakavakirwa pane yekutanga basa. Paunenge uchiisa zvinhu zvese zvedunhu, zvinotevera zvinofanirwa kusangana:

1. Ronga nzvimbo yega yega inoshanda yedunhu redhisheni maererano nekuyerera kwedunhu, kuitira kuti marongerwo ave nyore kutenderera kwechiratidzo, uye chiratidzo chinochengetwa munzira imwechete sezvazvinogona [1].

2. Take the core components of each functional unit as the center and lay out around him. The components should be uniformly, integrally and compactly arranged on the PCB to minimize and shorten the leads and connections between the components.

3. Pamasekete anoshanda pamafambiro akakwirira, kugovera parameters pakati pezvikamu zvinofanira kufungwa. Mumasekete mazhinji, zvikamu zvinofanirwa kurongeka zvakaenzana zvakanyanya sezvinobvira, izvo zvisiri kungonaka chete, asiwo zviri nyore kuisa uye nyore kugadzira kuwanda.

Maitiro ekugadzira uye kuongorora iyo PCB marongero

1. DFM requirements for layout

1. Nzira yakanyatsogadziriswa yakagadziriswa, uye zvigadziri zvese zvakaiswa pabhodhi.

2. The origin of the coordinates is the intersection of the left and lower extension lines of the board frame, or the lower left pad of the lower left socket.

3. The actual size of the PCB, the location of the positioning device, etc. are consistent with the process structure element map, and the device layout of the area with restricted device height requirements meets the requirements of the structure element map.

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5. Chimiro chekunze chebhodhi chine radian yakatsetseka ye 197mil, kana yakagadzirirwa maererano nekugadzirwa kwehukuru hwekugadzira.

6. Mabhodhi akajairika ane 200mil process edges; Kuruboshwe nekurudyi mativi ebackplane ane process edges yakakura kupfuura 400mil, uye ekumusoro neazasi mativi ane process edges anopfuura 680mil. Kuiswa kwemudziyo hakupesani nenzvimbo yekuvhura hwindo.

7. All kinds of additional holes (ICT positioning hole 125mil, handle bar hole, elliptical hole and fiber holder hole) that need to be added are all missing and set correctly.

8. Pini yepini yemudziyo, kutungamira kwemudziyo, kukwirira kwemudziyo, raibhurari yemudziyo, nezvimwewo zvakagadziriswa nemasaisai ekutengesa funga nezvezvinodiwa zvewave soldering.

9. The device layout spacing meets the assembly requirements: surface mount devices are greater than 20mil, IC is greater than 80mil, and BGA is greater than 200mil.

10. Zvikamu zvecrimping zvine anopfuura 120 mils muchikamu chepamusoro chinhambwe, uye hapana mudziyo munzvimbo yemukati meiyo crimping zvikamu panzvimbo yewelding.

11. Hapana michina mipfupi pakati pemidziyo mirefu, uye hapana chigamba midziyo uye pfupi uye diki interposing midziyo inoiswa mukati me5mm pakati pemidziyo ine hurefu hwakakura kupfuura 10mm.

12. Polar midziyo ine polarity silkscreen logos. Iyo X uye Y mafambiro emhando imwechete yepolarized plug-in zvikamu zvakafanana.

13. All devices are clearly marked, no P*, REF, etc. are not clearly marked.

14. Kune 3 yekuisa ma cursors pamusoro pepamusoro ine SMD zvishandiso, izvo zvakaiswa mu “L” chimiro. Nharaunda pakati pepakati penzvimbo yekumisikidza uye kumucheto kwebhodhi yakakura kupfuura 240 mils.

15. Kana iwe uchida kuita boarding processing, marongerwo anoonekwa sekufambisa kukwira uye PCB kugadzirisa uye kusangana.

16. Mipendero yakachekwa (mipendero isina kujairika) inofanira kuzadzwa nenzira yekugaya milling grooves uye maburi echitambi. Gomba rechitambi ibasa risina simbi, kazhinji 40 ms muhupamhi uye 16 ms kubva kumucheto.

17. The test points used for debugging have been added in the schematic diagram, and they are placed appropriately in the layout.

Chechipiri, iyo yekupisa dhizaini zvinodiwa zvekugadzirisa

1. Heating components and exposed components of the casing are not in close proximity to wires and heat-sensitive components, and other components should also be properly kept away.

2. The placement of the radiator takes into account the convection problem, and there is no interference of high components in the projection area of ​​the radiator, and the range is marked on the mounting surface with silk screen.

3. Mamiriro acho anofunga nezvezvinonzwisisika uye zvakatsetseka zvekupisa kupisa nzira.

4. I-electrolytic capacitor inofanira kuparadzaniswa zvakanaka kubva kune-high-heat device.

5. Funga nezvekupisa kwekupisa kwezvigadzirwa zvepamusoro-simba uye zvigadzirwa pasi pegusset.

Chechitatu, chiratidzo chekuvimbika zvinodiwa zvemarongerwo

1. The start-end matching is close to the sending device, and the end matching is close to the receiving device.

2. Place decoupling capacitors close to related devices

3. Place crystals, crystal oscillators and clock drive chips close to related devices.

4. High-speed uye yakaderera-speed, digital uye analog inorongwa zvakasiyana maererano nemamodules.

5. Sarudza iyo topological chimiro chebhazi zvichienderana nekuongorora uye simulation mhedzisiro kana chiitiko chiripo kuve nechokwadi chekuti zvinodiwa zvehurongwa zvinosangana.

6. If it is to modify the board design, simulate the signal integrity problem reflected in the test report and give a solution.

7. The layout of the synchronous clock bus system meets the timing requirements.

Zvina, EMC zvinodiwa

1. Inductive devices that are prone to magnetic field coupling, such as inductors, relays, and transformers, should not be placed close to each other. When there are multiple inductance coils, the direction is vertical and they are not coupled.

2. Kuti udzivise kukanganiswa kwemagetsi pakati pechigadzirwa chiri pawelding pamusoro pebhodhi rimwechete uye iri padyo nebhodhi rimwe chete, hapana michina inonzwisa tsitsi uye midziyo yakasimba yemwaranzi inofanirwa kuiswa pane welding pamusoro pebhodhi rimwe.

3. The interface components are placed close to the edge of the board, and appropriate EMC protection measures have been taken (such as shielding shells, hollowing out of the power supply ground, etc.) to improve the EMC capability of the design.

4. Dunhu redziviriro rinoiswa padhuze nedunhu rekuona, richitevera musimboti wekudzivirira kwekutanga wozosefa.

5. Kureba kubva kumuviri wekudzivirira uye ganda rekudzivirira kusvika kumuviri wekudzivirira uye ganda rekuvhara chivharo rinopfuura 500 mils yezvigadziri zvine simba rekutumira zvakanyanya kana kunyanya kunzwisisika (zvakadai secrystal oscillators, crystals, nezvimwewo).

6. A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong devices and signals.

Five, layer setting and power supply and ground division requirements

1. Kana mitsara miviri yechiratidzo yakatarisana zvakananga kune imwe neimwe, vertical wiring mitemo inofanira kutsanangurwa.

2. Mutambo mukuru wesimba uri pedyo nevhu rayo rinoenderana nepamusoro sezvinobvira, uye simba remagetsi rinosangana nekutonga kwe20H.

3. Each wiring layer has a complete reference plane.

4. Multi-layer boards ane laminated uye core material (CORE) inofananidzwa kudzivirira warping kunokonzerwa nekusaenzana kugoverwa kwemhangura yeganda density uye asymmetrical thickness yepakati.

5. Kuwanda kwebhodhi hakufaniri kudarika 4.5mm. Kune avo vane ukobvu hwakakura kupfuura 2.5mm (backplane yakakura kupfuura 3mm), nyanzvi dzinofanirwa kunge dzakasimbisa kuti hapana dambudziko nePCB kugadzirisa, kusangana, uye michina, uye PC kadhi bhodhi ukobvu i1.6mm.

6. Kana ukobvu-kusvika-dhayamita reshiyo yeVia yakakura kupfuura 10:1, inozosimbiswa nemugadziri wePCB.

7. The power and ground of the optical module are separated from other power and ground to reduce interference.

8. Simba uye kushandiswa kwepasi kwezvikamu zvakakosha zvinosangana nezvinodiwa.

9. Kana impedance control inodiwa, iyo layer setting parameter inosangana nezvinodiwa.

Six, power module requirements

1. Kurongeka kwechikamu chekugovera magetsi kunovimbisa kuti mitsetse yekupinza uye inobuda yakatsetseka uye haiyambuka.

2. Kana bhodhi rimwechete richipa simba kune subboard, isa inofananidzwa sefa yedunhu pedyo nemagetsi emagetsi ebhodhi rimwe chete uye simba rekupinza rebhokisi.

Zvinomwe, zvimwe zvinodiwa

1. Kurongeka kunotarisa kutsetseka kwese kwe wiring, uye iyo huru data inoyerera inonzwisisika.

2. Gadzirisa mapini ekugoverwa kwekusabatanidzwa, FPGA, EPLD, mutyairi webhazi uye zvimwe zvishandiso zvinoenderana nemhedzisiro yehurongwa kuti ukwidze marongero.

3. Kurongeka kunofunga nezvekuwedzera kwakakodzera kwenzvimbo pane dense wiring kudzivirira mamiriro ayo asingagoni kuendeswa.

4. Kana zvakakosha zvinhu, midziyo yakakosha (yakadai se0.5mmBGA, nezvimwewo), uye maitiro anokosha akagamuchirwa, nguva yekuendesa uye kugadziriswa kwakanyatsofungwa, uye yakasimbiswa nePCB vanogadzira uye vashandi vekugadzirisa.

5. Pini inoenderana nehukama hwegusset connector yakasimbiswa kudzivirira kutungamira uye kutaridzika kwegusset connector kubva pakudzorerwa shure.

6. If there are ICT test requirements, consider the feasibility of adding ICT test points during layout, so as to avoid difficulty in adding test points during the wiring phase.

7. When a high-speed optical module is included, the layout of the optical port transceiver circuit is prioritized.

8. Mushure mekunge marongerwo apera, dhirowa yegungano ye1: 1 yakapihwa kuti vashandi veprojekiti vatarise kana sarudzo yepasuru yemudziyo iri yechokwadi ichipikisana nechikamu chemudziyo.

9. Pakuvhura kwehwindo, ndege yemukati yakaonekwa seyakadzoserwa, uye nzvimbo yakakodzera yekurambidza wiring yakaiswa.