In design, layout is an important part. The quality of the layout result will directly affect the effect of the wiring, so it can be considered that a reasonable layout is the first step to a successful PCB design. Especially the pre-layout is the process of thinking about the entire circuit board, signal flow, heat dissipation, structure and other structures. If the pre-layout fails, no amount of effort will be needed.

PCB layout design The design process flow of printed circuit boards includes schematic design, electronic component database registration, design preparation, block division, electronic component configuration, configuration confirmation, wiring and final inspection. In the process of the process, no matter which process is found to be a problem, it must be returned to the previous process for reconfirmation or correction.

Sengoliloeng sena se qala ka ho tsebisa melao le mekhoa ea moralo oa PCB, ebe se hlalosa mokhoa oa ho rala le ho hlahloba sebopeho sa PCB, ho latela litlhoko tsa moralo oa DFM, litlhoko tsa moralo oa mocheso, litlhoko tsa botšepehi ba matšoao, litlhoko tsa EMC, litlhophiso tsa lera le litlhoko tsa karohano ea matla, le li-module tsa matla. Litlhoko le lintlha tse ling li tla hlahlojoa ka botlalo, ‘me u latele mohlophisi ho fumana lintlha.

Melao ea moralo oa PCB

1. Tlas’a maemo a tloaelehileng, likarolo tsohle li lokela ho hlophisoa sebakeng se le seng sa boto ea potoloho. Ke feela ha likarolo tsa boemo bo holimo li teteaneng haholo, moo lisebelisoa tse ling tse nang le bolelele bo fokolang le mocheso o fokolang, tse kang li-resistors, li-chip capacitor, le li-chip capacitor, li ka kenngoa. Chip IC, joalo-joalo li behoa lera le ka tlaase.

2. Tlas’a motheo oa ho netefatsa ts’ebetso ea motlakase, likaroloana li lokela ho behoa holim’a marang-rang le ho hlophisoa ka tsela e tšoanang kapa ea perpendicular ho e mong e le hore e be makhethe le e ntle. Tlas’a maemo a tloaelehileng, likarolo ha lia lumelloa ho kopana; tlhophiso ea likarolo e lokela ho ba e kopanetsoeng, ‘me likarolo li lokela ho hlophisoa holim’a sebopeho sohle. Kabo e tšoana ebile e teteaneng.

3. The minimum distance between adjacent land patterns of different components on the circuit board should be above 1mm.

4. Sebaka ho tloha moeling oa boto ea potoloho ka kakaretso ha se ka tlase ho 2MM. Sebopeho se setle ka ho fetisisa sa boto ea potoloho ke khutlonnetsepa, ‘me karolo ea likarolo ke 3: 2 kapa 4: 3. Ha boholo ba boto ea potoloho bo le kholo ho feta 200MM ka 150MM, nahana ka seo boto ea potoloho e ka mamellang matla a Mechanical.

PCB layout design skills

Moqaping oa sebopeho sa PCB, likarolo tsa boto ea potoloho li lokela ho hlahlojoa, ‘me moralo oa moralo o lokela ho ipapisa le ts’ebetso ea ho qala. Ha ho etsoa likarolo tsohle tsa potoloho, melao-motheo e latelang e lokela ho finyelloa:

1. Lokisetsa boemo ba mochine o mong le o mong oa potoloho o sebetsang ho ea ka potoloho ea potoloho, e le hore mohaho o be o loketseng bakeng sa ho potoloha ha pontšo, ‘me letšoao le bolokoe ka tsela e tšoanang ka hohle kamoo ho ka khonehang [1].

2. Take the core components of each functional unit as the center and lay out around him. The components should be uniformly, integrally and compactly arranged on the PCB to minimize and shorten the leads and connections between the components.

3. Bakeng sa lipotoloho tse sebetsang ka maqhubu a phahameng, litekanyetso tsa kabo pakeng tsa likarolo li tlameha ho nkoa. Lipotolohong tse akaretsang, likarolo li lokela ho hlophisoa ka mokhoa o ts’oanang ka hohle kamoo ho ka khonehang, e seng e ntle feela, empa hape e bonolo ho kenya le ho le bonolo ho hlahisa lihlahisoa tse ngata.

Mokhoa oa ho rala le ho hlahloba sebopeho sa PCB

1. DFM requirements for layout

1. Tsela e nepahetseng ea ts’ebetso e khethiloe, ‘me lisebelisoa tsohle li behiloe botong.

2. The origin of the coordinates is the intersection of the left and lower extension lines of the board frame, or the lower left pad of the lower left socket.

3. The actual size of the PCB, the location of the positioning device, etc. are consistent with the process structure element map, and the device layout of the area with restricted device height requirements meets the requirements of the structure element map.

4. Sebaka sa mochine oa ho daela, sesebelisoa sa ho tsosolosa, leseli la pontšo, joalo-joalo se loketse, ‘me mohala oa ho tšoara ha o kena-kenane le lisebelisoa tse potolohileng.

5. Foreimi e ka ntle ea boto e na le radian e boreleli ea 197mil, kapa e entsoe ho latela setšoantšo sa boholo ba sebopeho.

6. Liboto tse tloaelehileng li na le 200mil process edges; mahlakoreng a ho le letšehali le a ka ho le letona a sefofane se ka morao a na le likarolo tse kholo ho feta 400mil, ‘me mahlakoreng a ka holimo le a ka tlaase a na le likarolo tse kholo ho feta 680mil. Ho beoa ha sesebelisoa ha ho hohlane le boemo ba fensetere e butsoeng.

7. All kinds of additional holes (ICT positioning hole 125mil, handle bar hole, elliptical hole and fiber holder hole) that need to be added are all missing and set correctly.

8. Pin pitch ea sesebelisoa, tataiso ea sesebelisoa, molumo oa sesebelisoa, laebrari ea lisebelisoa, joalo-joalo tse sebetsitsoeng ka ho ferekanngoa ha maqhubu li nahanela litlhoko tsa maqhubu a motlakase.

9. The device layout spacing meets the assembly requirements: surface mount devices are greater than 20mil, IC is greater than 80mil, and BGA is greater than 200mil.

10. Likarolo tsa crimping li na le limilimithara tse fetang 120 sebakeng se bohōle ba karolo, ‘me ha ho na sesebelisoa sebakeng sa likarolo tsa crimping sebakeng sa welding.

11. Ha ho na lisebelisoa tse khutšoanyane pakeng tsa lisebelisoa tse telele, ‘me ha ho lisebelisoa tsa patch le lisebelisoa tse khutšoanyane le tse nyenyane tse kenang ka hare ho 5mm pakeng tsa lisebelisoa tse nang le bolelele bo fetang 10mm.

12. Lisebelisoa tsa polar li na le li-logo tsa polarity silkscreen. Litaelo tsa X le Y tsa mofuta o tšoanang oa likarolo tsa polarized plug-in lia tšoana.

13. All devices are clearly marked, no P*, REF, etc. are not clearly marked.

14. Ho na le li-cursor tsa 3 tsa boemo bo holimo tse nang le lisebelisoa tsa SMD, tse behiloeng ka sebopeho sa “L”. Sebaka se pakeng tsa bohareng ba sesupo sa boemo le moeli oa boto se seholo ho feta 240 mils.

15. Haeba o hloka ho etsa ts’ebetso ea bolulo, sebopeho se nkoa e le ho nolofatsa ts’ebetso ea ho palama le PCB le kopano.

16. Mets’epe e chehiloeng (mathōko a sa tloaelehang) a lokela ho tlatsoa ka li-grooves tsa ho sila le masoba a setempe. Lesoba la setempe ke sekheo se se nang tšepe, ka kakaretso bophara ba limilimithara tse 40 le limilimithara tse 16 ho tloha pheletsong.

17. The test points used for debugging have been added in the schematic diagram, and they are placed appropriately in the layout.

Ea bobeli, litlhoko tsa moralo oa mocheso oa sebopeho

1. Heating components and exposed components of the casing are not in close proximity to wires and heat-sensitive components, and other components should also be properly kept away.

2. The placement of the radiator takes into account the convection problem, and there is no interference of high components in the projection area of ​​the radiator, and the range is marked on the mounting surface with silk screen.

3. Sebopeho se nahanela mekhoa e utloahalang le e boreleli ea ho senya mocheso.

4. The electrolytic capacitor e lokela ho aroloa hantle ho tloha mochine o chesang haholo.

5. Nahana ka ho senyeha ha mocheso oa lisebelisoa tse matla le lisebelisoa tse tlas’a gusset.

Ea boraro, litlhoko tsa botšepehi ba pontšo ea moralo

1. The start-end matching is close to the sending device, and the end matching is close to the receiving device.

2. Place decoupling capacitors close to related devices

3. Place crystals, crystal oscillators and clock drive chips close to related devices.

4. Lebelo le phahameng le le tlaase, digital le analog li hlophisitsoe ka thoko ho latela li-module.

5. Etsa qeto ea sebopeho sa topological sa bese ho latela liphetho tsa tlhahlobo le papiso kapa phihlelo e teng ho netefatsa hore litlhoko tsa tsamaiso li finyelloa.

6. If it is to modify the board design, simulate the signal integrity problem reflected in the test report and give a solution.

7. The layout of the synchronous clock bus system meets the timing requirements.

Tse ‘nè, litlhoko tsa EMC

1. Inductive devices that are prone to magnetic field coupling, such as inductors, relays, and transformers, should not be placed close to each other. When there are multiple inductance coils, the direction is vertical and they are not coupled.

2. E le ho qoba ho kena-kenana le motlakase pakeng tsa sesebelisoa se holim’a tjheseletsa ea boto e le ‘ngoe le boto e le ‘ngoe e haufi, ha ho lisebelisoa tse hlokolosi le lisebelisoa tse matla tsa mahlaseli tse lokelang ho behoa holim’a welding holim’a boto e le’ ngoe.

3. The interface components are placed close to the edge of the board, and appropriate EMC protection measures have been taken (such as shielding shells, hollowing out of the power supply ground, etc.) to improve the EMC capability of the design.

4. Potoloho ea tšireletso e behoa haufi le potoloho ea li-interface, ho latela molao-motheo oa tšireletso ea pele ebe o sefa.

5. Sebaka se tsoang ho ‘mele o sireletsang le khetla e sireletsang ho ea ho’ mele o sireletsang le khetla ea sekoahelo se sireletsang ho feta 500 mils bakeng sa lisebelisoa tse nang le matla a phahameng a ho fetisa kapa ka ho khetheha tse hlokolosi (tse kang crystal oscillators, crystals, joalo-joalo).

6. A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong devices and signals.

Five, layer setting and power supply and ground division requirements

1. Ha likarolo tse peli tsa lipontšo li bapile ka ho toba, melao ea wiring e otlolohileng e tlameha ho hlalosoa.

2. Lera le leholo la matla le haufi le sebaka sa eona sa fatše se lumellanang ka hohle kamoo ho ka khonehang, ‘me matla a matla a kopana le molao oa 20H.

3. Each wiring layer has a complete reference plane.

4. Mapolanka a marang-rang a mangata a laminated ‘me lisebelisoa tsa mantlha (CORE) li lekana ho thibela ntoa e bakoang ke ho arola ho sa tšoaneng ha letlalo la koporo le botenya ba asymmetrical ea bohareng.

5. Botenya ba boto ha boa lokela ho feta 4.5mm. Bakeng sa ba nang le botenya bo fetang 2.5mm (backplane e kholo ho feta 3mm), litsebi li ne li lokela ho tiisa hore ha ho na bothata ka ts’ebetso ea PCB, kopano le lisebelisoa, ‘me botenya ba karete ea PC ke 1.6mm.

6. Ha karo-karolelano ea botenya-to-diameter ea via e kholo ho feta 10: 1, e tla tiisoa ke moetsi oa PCB.

7. The power and ground of the optical module are separated from other power and ground to reduce interference.

8. Matla le ts’ebetso ea fatše ea likarolo tsa bohlokoa li finyella litlhoko.

9. Ha taolo ea impedance e hlokahala, litekanyetso tsa ho beha lera li finyella litlhoko.

Six, power module requirements

1. The layout of the power supply part ensures that the input and output lines are smooth and do not cross.

2. Ha boto e le ‘ngoe e fana ka matla ho subboard, beha potoloho ea filthara e lumellanang haufi le motlakase oa boto e le’ ngoe le motlakase oa motlakase oa subboard.

Seven, other requirements

1. Sebopeho se nahanela ho boreleli ka kakaretso ha mohala, ‘me phallo e kholo ea data e utloahala.

2. Fetola likabelo tsa phini tsa khaollo, FPGA, EPLD, mokhanni oa libese le lisebelisoa tse ling ho latela liphetho tsa moralo ho ntlafatsa moralo.

3. Sebopeho se nahanela ho eketseha ho loketseng ha sebaka ho lithapo tse teteaneng ho qoba boemo ba hore bo ke ke ba tsamaisoa.

4. Haeba lisebelisoa tse khethehileng, lisebelisoa tse khethehileng (tse kang 0.5mmBGA, joalo-joalo), le mekhoa e khethehileng e amoheloa, nako ea pelehi le ts’ebetso ea ts’ebetso li ‘nile tsa nkoa ka botlalo,’ me li netefalitsoe ke baetsi ba PCB le basebetsi ba ts’ebetso.

5. Kamano e tsamaellanang ea pin ea sehokelo sa gusset e tiisitsoe ho thibela tataiso le tšekamelo ea sehokelo sa gusset hore li se ke tsa fetoloa.

6. If there are ICT test requirements, consider the feasibility of adding ICT test points during layout, so as to avoid difficulty in adding test points during the wiring phase.

7. When a high-speed optical module is included, the layout of the optical port transceiver circuit is prioritized.

8. Ka mor’a hore moralo o phethoe, ho fanoe ka setšoantšo sa kopano ea 1: 1 bakeng sa basebetsi ba morero ho hlahloba hore na khetho ea sephutheloana sa lisebelisoa e nepahetse khahlanong le mokhatlo oa lisebelisoa.

9. Ha ho buloa fensetere, sefofane se ka hare se ‘nile sa nkoa e le se khutlisitsoeng,’ me ho behiloe sebaka se loketseng sa thibelo ea lithapo.