Through the analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. PCB platasidagi signal izlarining qatlamlarini o’zgartirmaslikka harakat qiling, ya’ni keraksiz vialardan foydalanmaslikka harakat qiling.

4. Quvvat va tuproqli pinlar yaqin joyda burg’ulash kerak, va vites va pin o’rtasidagi qo’rg’oshin imkon qadar qisqa bo’lishi kerak, chunki ular indüktansni oshiradi. Shu bilan birga, quvvat va tuproq simlari impedansni kamaytirish uchun imkon qadar qalin bo’lishi kerak.

5. Signal uchun eng yaqin halqani ta’minlash uchun signal qatlamining yo’llari yaqiniga bir necha tuproqli viyalarni joylashtiring. Hatto PCB platasiga ko’p miqdorda keraksiz tuproqli viteslarni joylashtirish mumkin. Albatta, dizayn moslashuvchan bo’lishi kerak. Yuqorida muhokama qilingan via modeli har bir qatlamda prokladkalar mavjud bo’lgan holatdir. Ba’zan, biz ba’zi qatlamlarning yostiqlarini kamaytirishimiz yoki hatto olib tashlashimiz mumkin. Ayniqsa, viyalarning zichligi juda yuqori bo’lsa, bu mis qatlamidagi pastadirni ajratib turadigan uzilish yivining shakllanishiga olib kelishi mumkin. Bu muammoni hal qilish uchun, via o’rnini siljitishdan tashqari, mis qatlamiga via o’rnatishni ham ko’rib chiqishimiz mumkin. Plitalar hajmi kamayadi.