Through the analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. Gbiyanju lati ma yi awọn ipele ti awọn itọpa ifihan agbara pada lori igbimọ PCB, iyẹn ni lati sọ, gbiyanju lati ma lo nipasẹs ti ko wulo.

4. Agbara ati awọn pinni ilẹ yẹ ki o wa ni ti gbẹ iho nitosi, ati asiwaju laarin nipasẹ ati pin yẹ ki o jẹ kukuru bi o ti ṣee ṣe, nitori pe wọn yoo mu inductance sii. Ni akoko kanna, agbara ati awọn itọsọna ilẹ yẹ ki o nipọn bi o ti ṣee ṣe lati dinku ikọlu.

5. Gbe diẹ ninu awọn vias ilẹ legbe awọn vias ti awọn ifihan agbara Layer lati pese awọn sunmọ lupu fun awọn ifihan agbara. O ti wa ni ani ṣee ṣe lati gbe kan ti o tobi nọmba ti laiṣe ilẹ vias lori PCB ọkọ. Dajudaju, apẹrẹ naa nilo lati rọ. Awọn nipasẹ awoṣe sísọ sẹyìn ni irú ibi ti o wa ni o wa paadi lori kọọkan Layer. Nigba miiran, a le dinku tabi paapaa yọ awọn paadi ti awọn fẹlẹfẹlẹ kan kuro. Paapa nigbati iwuwo ti vias ba ga pupọ, o le ja si dida iho fifọ ti o ya lupu ni Layer Ejò. Lati yanju iṣoro yii, ni afikun si gbigbe ipo ti nipasẹ, a tun le ronu gbigbe nipasẹ lori Layer Ejò. Iwọn paadi ti dinku.