In PCB hoʻolālā, ESD kūʻē o PCB hiki ke hoʻokō ʻia ma o ka layering, hoʻonohonoho pono a me ka hoʻonohonoho ʻana. Ma ke kaʻina hoʻolālā, hiki i ka hapa nui o nā hoʻololi hoʻolālā ke kaupalena ʻia i ka hoʻohui a wehe ʻana paha i nā mea ma o ka wanana. Ma ka hoʻoponopono ʻana i ka ʻōnaehana PCB a me nā uea, hiki ke pale maikaʻi ʻia ʻo ESD.

Uila uila mai ke kino o ke kanaka, ke kaiapuni a hiki i loko o nā uila uila hiki ke hana i nā hōʻino like ʻole i nā ʻāpana semiconductor kikoʻī, e like me ke komo ʻana i ka papa hoʻoluʻu lahilahi i loko o nā mea; Poino i nā puka pā o MOSFET a me CMOS mau mea; Hoʻokomo i ka laka ma ka hāmeʻa CMOS; Pōkole ke kaapuni huli hope PN huina; Pōkole ke kaapuni maikaʻi bias PN hui; E hoʻoheheʻe i ka uea wili a i ʻole ka uea aluminika i loko o ka hāmeʻa hana. I mea e hoʻopau ai i ka hoʻopilikia a me ka hōʻino ʻana o ka hoʻokuʻu electrostatic (ESD) i nā pono uila, pono e lawe i nā ʻano hana loea e pale ai.

How to enhance anti-ESD function in PCB design

In the design of PCB board, anti-ESD design of PCB can be realized through layering, proper layout and installation. Ma ke kaʻina hoʻolālā, hiki i ka hapa nui o nā hoʻololi hoʻolālā ke kaupalena ʻia i ka hoʻohui a wehe ʻana paha i nā mea ma o ka wanana. Ma ka hoʻoponopono ʻana i ka ʻōnaehana PCB a me nā uea, hiki ke pale maikaʻi ʻia ʻo ESD. Eia kekahi mau akahele maʻamau.

Use multilayer PCBS whenever possible. The ground and power planes, as well as the tightly spaced signal line-ground lines, can reduce common-mode impedance and inductive coupling to 1/10 to 1/100 of a double-sided PCB compared to a double-sided PCB. E hoʻāʻo e kau i kēlā me kēia papa hōʻailona kokoke i kahi papa mana a lepo paha. No ka PCBS kiʻekiʻena kiʻekiʻe me nā ʻāpana o ka papa luna a me lalo, nā pilina pōkole loa, a me ka nui o ka hoʻopihapiha honua, e noʻonoʻo e hoʻohana i nā laina o loko.

For double-sided PCBS, tightly interwoven power supplies and grids are used. Aia ke kaula uila i ka honua a pili pono e like me ka hiki ma waena o nā laina kaulike a me nā laina ākea a i ʻole nā ​​zona hoʻopiha. E emi ka nui o ka ʻaoʻao o hoʻokahi ʻaoʻao a i ʻole 60mm paha, a i ʻole 13mm ma lalo inā hiki.

Make sure each circuit is as compact as possible.

Put all connectors aside as much as possible.

If possible, direct the power cord from the center of the card away from areas that are directly exposed to ESD.

On all PCB layers below the connector leading out of the case (prone to direct ESD hits), place wide chassis or polygon filled floors and connect them together with holes at approximately 13mm intervals.

Mounting holes are placed on the edge of the card, and the top and bottom pads of open flux are connected to the floor of the chassis around the mounting holes.

When assembling PCB, do not apply any solder on top or bottom pad. E hoʻohana i nā wili me nā mea holoi i kūkulu ʻia e hāʻawi i ka pilina paʻa ma waena o PCB a me nā chassis / pale kila a kākoʻo paha i ka papa honua.

The same “isolation zone” should be set up between the chassis floor and the circuit floor on each layer; Inā hiki, mālama i ka spacing ma 0.64mm.

At the top and bottom of the card near the mounting hole, connect the chassis ground and the circuit ground with 1.27mm wide wires every 100mm along the chassis ground wire. Pili i kēia mau kiko pili, kahi pad a i ʻole ka lua e kau ai no ka hoʻonoho ʻana i kau ma waena o ka honua chassis a me ka honua kaapuni. Hiki keʻokiʻoki i kēia mau pilina honua me ka pahi e hāmama, a i ʻole lele i nā lei manamana / nā capacitors pinepine.

If the circuit board will not be placed in a metal chassis or shielding device, the top and bottom chassis ground wire of the circuit board can not be coated with solder resistance, so that they can be used as ESD arc discharge electrode.

A ring is set around the circuit in the following manner:

(1) Ma waho aʻe o ka hoʻopili o ka lihi a me ka chassis, ke ākea āpau o ke komo ʻana o ke apo.

(2) E hōʻoia i ka laulā o nā papa āpau i ʻoi aku ma mua o 2.5mm.

(3) Pili nā lua i ke apo i kēlā me kēia 13mm.

(4) E hoʻohui i ka honua annular a me ka honua maʻamau o ka puni ākea multi-layer.

(5) No nā pale pālua i kau ʻia i nā hihia metala a i ʻole nā ​​pale pale, e hoʻopili ʻia ka pae o ke apo i ka papa maʻamau o ke kaapuni. Pono e hoʻopili ʻia ke kaapuni ʻelua ʻaoʻao ʻole i ka lepo o ke apo, ʻaʻole pono e uhi ʻia ke kahua apo me ka flx, i hiki i ke kahua apo ke hana ma ke ʻano he koʻokoʻo hoʻokuʻu ESD, ma kahi o kahi ākea 0.5mm ākea ma ka pae o ke apo (āpau papa), i mea e hiki ai ke hōʻalo i kahi loop nui. ʻAʻole pono ka emi o nā kelepaʻi hōʻailona ma lalo o 0.5mm mai ke kahua o ke apo.