Pehea e kaohi ai PCB impedance?

Without impedance control, considerable signal reflection and distortion will be caused, resulting in design failure. Common signals, such as PCI bus, PCI-E bus, USB, Ethernet, DDR memory, LVDS signal, etc., all need impedance control. Impedance control ultimately needs to be realized through PCB design, which also puts forward higher requirements for PCB board technology. After communication with PCB factory and combined with the use of EDA software, the impedance of wiring is controlled according to the requirements of signal integrity.

Hiki ke helu ʻia i nā ʻano uila e loaʻa ai ka waiwai impedance like.

Microstrip lines

• Aia kahi o ka uea me ka mokulele honua a me dielectric i waenakonu. Inā kū mau ka dielectric, ka laulā o ka laina, a me kona mamao mai ka mokulele honua kaohi, a laila hiki ke kaohi ʻia kona ʻano impedance, a aia ka pololei ma waena o 5%.

What is impedance control how to perform impedance control on PCB

Laina

ʻO kahi laina lipine kahi kaula keleawe i waenakonu o ka dielectric ma waena o nā mokulele alakaʻi ʻelua. If the thickness and width of the line, the dielectric constant of the medium, and the distance between the ground planes of the two layers are controllable, the characteristic impedance of the line is controllable, and the accuracy is within 10%.

What is impedance control how to perform impedance control on PCB

The structure of multi-layer board:

I mea e kaohi pono ai i ka impedance PCB, pono e hoʻomaopopo i ke ʻano o PCB:

ʻO ka mea maʻamau a mākou i kapa aku ai he papa multilayer i hana ʻia me ka pā nui a me ka pepa laminated semi-solidified pū kekahi me kekahi. ʻO ka papa Core he paʻakikī, mānoanoa kikoʻī, ʻelua pā keleawe berena, ʻo ia ka mea maʻa o ka papa pai. And the semi-cured piece constitutes the so-called infiltration layer, plays the role of bonding the core plate, although there is a certain initial thickness, but in the process of pressing its thickness will occur some changes.

ʻO ka maʻa mau ʻo nā papa dielectric ʻelua o ka multilayer i pulu ʻia, a hoʻohana ʻia nā papa keleawe keleawe ma waho o kēia mau papa ʻelua e like me ka pepa keleawe waho. ʻO ke kikoʻī o ka mānoanoa o ka pepa keleawe o waho a me ka foil keleawe o loko he 0.5oz, 1OZ, 2OZ (ʻo 1OZ e pili ana i 35um a i ʻole 1.4mil), akā ma hope o ke kaʻina o ka mālama ʻana i ka papa, e hoʻonui ka mānoanoa hope loa o nā pepa keleawe waho e pili ana. 1OZ. ʻO ka pepa keleawe o loko ka uhi keleawe ma nā ʻaoʻao ʻelua o ka pā nui. ʻOkoʻa iki ka mānoanoa hope loa i ka mānoanoa kumu, akā hoʻemi ʻia ia e kekahi mau um ma muli o ka hoʻopaʻa ʻana.

The outermost layer of the multilayer board is the welding resistance layer, which is what we often say “green oil”, of course, it can also be yellow or other colors. The thickness of the solder resistance layer is generally not easy to determine accurately. The area without copper foil on the surface is slightly thicker than the area with copper foil, but because of the lack of copper foil thickness, so the copper foil is still more prominent, when we touch the printed board surface with our fingers can feel.

Ke hana ʻia kahi mānoanoa o ka papa paʻi, ma kekahi lima, koi ʻia nā koho kūpono o nā mea kikoʻī, ma ka ʻaoʻao ʻē aʻe, e ʻoi aku ka liʻiliʻi o ka mānoanoa hope loa o ka pepa semi-cured ma mua o ka mānoanoa mua. The following is a typical 6-layer laminated structure:

What is impedance control how to perform impedance control on PCB

PCB parameters:

Different PCB plants have slight differences in PCB parameters. Through communication with circuit board plant technical support, we obtained some parameter data of the plant:

ʻO ka pepa kila keleawe:

There are three thicknesses of copper foil that can be used: 12um, 18um and 35um. ʻO ka mānoanoa hope loa ma hope o ka pau ʻana ma kahi o 44um, 50um a me 67um.

Core plate: S1141A, standard FR-4, two breaded copper plates are commonly used. The optional specifications can be determined by contacting the manufacturer.

Semi-cured tablet:

Specifications (original thickness) are 7628 (0.185mm), 2116 (0.105mm), 1080 (0.075mm), 3313 (0.095mm). The actual thickness after pressing is usually about 10-15um less than the original value. Hiki ke hoʻohana ʻia i kahi kiʻekiʻena o 3 mau papa semi-cured no ka papa infiltration like, a ʻaʻole hiki ke like ka mānoanoa o 3 papa semi-cured, ma kahi o hoʻokahi hapalua i hoʻōla ʻia e hoʻohana ʻia nā papa, akā pono e hoʻohana kekahi mau mea hana i ʻelua mau mea. . If the thickness of the semi-cured piece is not enough, the copper foil on both sides of the core plate can be etched off, and then the semi-cured piece can be bonded on both sides, so that a thicker infiltration layer can be achieved.

Resistance welding layer:

ʻO ka mānoanoa o ka pale solder e pale i ka pepa keleawe ʻo C2≈8-10um. ʻO ka mānoanoa o ka solder resist layer ma ka ʻaoʻao me ka ʻole o ka foil keleawe ʻo C1, ka mea ʻokoʻa me ka mānoanoa o ke keleawe ma luna. Ke kū ka mānoanoa o ke keleawe ma luna o 45um, C1≈13-15um, a ke 70um ka mānoanoa o ke keleawe, C1≈17-18um.

Traverse section:

E noʻonoʻo mākou ʻo ka ʻāpana keʻa o ka uea he huinahā lōʻihi, akā he trapezoid maoli ia. Taking the TOP layer as an example, when the thickness of copper foil is 1OZ, the upper bottom edge of trapezoid is 1MIL shorter than the lower bottom edge. ʻO kahi laʻana, inā ʻo 5MIL ka laulā o ka laina, a laila ʻo ka ʻaoʻao luna a me lalo e pili ana i 4MIL a ʻo ka ʻaoʻao lalo a me lalo e pili ana iā 5MIL. The difference between top and bottom edges is related to copper thickness. The following table shows the relationship between top and bottom of trapezoid under different conditions.

What is impedance control how to perform impedance control on PCB

ʻAeʻae: ʻO ka ʻae ʻana o nā pale semi-cured e pili ana i ka mānoanoa. Hōʻike ka papa aʻe i ka mānoanoa a me ka palena o ka ʻae ʻana o nā ʻano like ʻole o nā pale semi-cured.

What is impedance control how to perform impedance control on PCB

The dielectric constant of the plate is related to the resin material used. The dielectric constant of FR4 plate is 4.2 — 4.7, and decreases with the increase of frequency.

ʻO ke kumu pohō dielectric: nā mea dielectric ma lalo o ka hana o ka alternating kahua uila, ma muli o ka wela a me ka hoʻohana ʻana o ka ikehu i kapa ʻia he dielectric loss, i hōʻike pinepine ʻia e ka mea pohō dielectric Tan δ. ʻO ka waiwai maʻamau no S1141A ka 0.015.

Ka liʻiliʻi o ka laina laina a me ka spacing line e hōʻoia i ka mīkini ʻana: 4mil / 4mil.

Hoʻokomo i ka pono hana helu helu Impedance:

Ke hoʻomaopopo mākou i ke ʻano o ka papa multilayer a haku i nā palena i makemake ʻia, hiki iā mākou ke helu i ka impedance ma o ka polokalamu EDA. Hiki iā ʻoe ke hoʻohana iā Allegro e hana i kēia, akā paipai wau iā Polar SI9000, kahi mea hana maikaʻi no ka helu ʻana i ka impedance ʻano a hoʻohana ʻia e nā hale hana PCB he nui.

Ke helu nei i ka impedance ʻano o ka hōʻailona o loko o ka laina ʻokoʻa a me ka laina laina hoʻokahi, e ʻike ʻoe i kahi ʻokoʻa iki ma waena o Polar SI9000 a me Allegro ma muli o kekahi mau kikoʻī, e like me ke ʻano o ka ʻāpana keʻa o ka uea. Eia nō naʻe, inā e helu ia i ka impedance ʻano o ka hōʻailona Surface, ke ʻōlelo nei wau e koho ʻoe i ke kope i uhi ʻia ma kahi o ka hiʻohiʻona Surface, no ka mea ʻo ia mau hiʻohiʻona e noʻonoʻo i ka noho ʻana o ka papa pale pale solder, no laila ʻoi aku ka pololei o nā hopena. The following is a partial screenshot of the surface differential line impedance calculated with Polar SI9000 considering the solder resistance layer:

What is impedance control how to perform impedance control on PCB

ʻOiai ʻaʻole maʻalahi ka mānoanoa o ka pale solder resist, hiki ke hoʻohana ʻia i kahi ala kokoke, e like me ka ʻōlelo a ka mea hana papa: e unuhi i kahi waiwai kikoʻī mai ka helu hoʻohālikelike Surface. Paipai ʻia ka hoʻemi ʻia o ka impedance ʻokoʻa ma kahi o 8 ohm a ʻo ka impedance hoʻokahi hopena e lawe ʻia i 2 ohm.

Nā koi PCB ʻokoʻa no ka uea ʻana

(1) E hoʻoholo i ke ʻano uila, nā palena a me ka helu impedance. Aia he ʻelua ʻano ʻokoʻa ʻokoʻa no ke kaʻina laina: ʻo ka ʻokoʻa ʻokoʻa laina laina microstrip waho a me ka ʻokoʻa laina laina ʻaoʻao o loko. Hiki ke helu ʻia ka imppedance e ka polokalamu hoʻohelu impedance pili (e like me POLAR-SI9000) a i ʻole ka impedance calculation formula ma o ka hoʻonohonoho pono parameter.

(2) Nā lālani isometric like. E hoʻoholo i ka laulā a me ka spacing, a hāhai pono i ka laulā laina i helu ʻia a me ka spacing i ka wā e hele ana. ʻO ka hoʻokaʻawale ma waena o nā laina ʻelua e noho mau i ka hoʻololi ʻole, ʻo ia hoʻi, e hoʻomau i ka like. There are two ways of parallelism: one is that the two lines walk in the same side-by-side layer, and the other is that the two lines walk in the over-under layer. E hoʻāʻo maʻamau e hōʻole i ka hoʻohana ʻana i ka hōʻailona ʻokoʻa ma waena o nā papa, ʻo ia hoʻi no ka hana maoli ʻana o PCB i ke kaʻina hana, ma muli o ka cascading laminated alignment ʻoi aku ka haʻahaʻa ma mua o ka mea i hāʻawi ʻia ma waena o ka kikoʻī a me ka hana o ka laminated dielectric loss, ʻaʻole hiki ke hōʻoia i ka hoʻokaʻawale ʻana i ka laina laina i ka mānoanoa o ka dilayer uila, e hana i ka ʻokoʻa ma waena o nā papa o ka ʻokoʻa o ka hoʻololi impedance. Paipai ʻia e hoʻohana i ka ʻokoʻa ma waena o ka papa like e like me ka hiki.