Papa PCB hōʻuluʻulu manaʻo ʻike:

(1): Ke kahakaha ʻana i ke kiʻikuhi hoʻolālā, pono ka annotation o ka pin e hoʻohana i ka pūnaewele NET ma mua o ka ʻōlelo, a i ʻole inā e loaʻa nā pilikia i ke alakaʻi ʻana i ka hoʻolālā PCB.

(2): Ke kahakaha ʻana i ke kiʻikuhi hoʻolālā, pono mākou e hana i nā ʻāpana āpau i ka hoʻopili ʻana, inā ʻaʻole ʻike ʻia nā ʻāpana i ke alakaʻi ʻana i ka PCB.

ʻAʻole hiki ke loaʻa kekahi mau mea i ka waihona no ka huki ʻana i kā lākou iho, ʻo ka ʻoiaʻiʻo, maikaʻi ke kahakiʻi i kā lākou iho, a loaʻa ka waihona i hope, maʻalahi kēlā. E kapa hou i kahi hui, e hoʻomaka i ka faila / NEW – koho iā SK LIB – e komo i ka waihona waihona ʻĀpana.

ʻO ka ʻōkuhi o ka pūʻulu e like me kēia, akā koho i ka PCB LIB, a aia ka palena o ka mea i ka TOPOverlay layer, he melemele ia.

(3) No ka inoa hou o nā mea i ke kaʻina, koho i nā MEA —a ANNOTATE i ka ANNOTATE annotation a koho i ke kauoha

(4): ma mua o ka hoʻololi ʻana i PCB, e hana i nā hōʻike, ʻo ka nui o ka papa ʻaina pūnaewele koho DESIGN DESIGN – “Hana Netlist e hana i ka papa ʻaina pūnaewele.

(5): Aia kekahi e nānā i nā lula uila: koho i nā mea hana ->>; ERC

(6): A laila hiki iā PCB ke hana. Inā loaʻa kekahi hemahema i ke kaʻina hanauna, pono e hoʻoponopono pono ʻia ke kiʻikuhi kiʻi a hana hou ʻia i PCB

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(8): Hoʻolālā i nā lula ma mua o ke kaha kiʻi ʻana i nā laina: Nā mea hana – Hoʻolālā i nā Lula, RouTIng Constrain GAP 10 a i ʻole 12, RouTIng VIA STYLE i hoʻonohonoho i ka puka, ke anawaena kūwaho kūwaho, ka palena iki o ke anawaena kūwaho, Ka nui o ka palena iki o ke anawaena o loko. Hoʻonohonoho ka palena ākea i ka laina ka laulā, Max a me min

(9): ʻO ka laulā o ka laina kaha kiʻi 12MIL, kahi pōʻai o ka lako a me ka uea honua 120 a 100 paha, ʻo ka lako a me ka honua o ke kiʻi he 50 a 40 a 30 paha, e mānoanoa ka uea aniani, e kau ʻia ma ka aʻe i ka microcomputer chip chip hoʻokahi, pono ka mānoanoa o ka laina lehulehu, mānoanoa ka laina lōʻihi, ʻaʻole hiki i ka laina ke hoʻohuli i ka Angle pono i 45 kekelē, pono ka māka o ka mana a me ka lepo a me nā hōʻailona ʻē aʻe i TOPLAY. ʻO ke kaula uila maʻalahi.

Inā ʻike ʻoe ʻaʻole pololei ke kiʻikuhi, pono ʻoe e hoʻololi mua i ke kiʻikuhi kiʻi, a laila e hoʻohana i ke kiʻikuhi e hoʻololi i ka PCB.

(10): Hiki ke hoʻonohonoho i ka koho o lalo o ka koho VIEW i ka ʻīniha a i ka millimeter.

(11): I mea e hoʻomaikaʻi ai i ka anti-interferensi o ka papa, ʻoi aku ka maikaʻi o ka hoʻopili ʻana i ke keleawe, koho i ke keleawe keleawe, ʻike ʻia kahi pahu kamaʻilio, Net OpTIon ma ke kiʻi e koho i ka pūnaewele i hoʻopili ʻia, a me nā koho ʻelua ma lalo pono e koho ʻia, HATCHING STYLE, koho i ke ʻano o ka uhi keleawe, kēia koho. ʻO GRID SIZE ka wahi ma waena o nā kuhi GRID keleawe, a ʻo TRACK WIDTH e kūlike me ka laina WIDTH o kā mākou PCB. Hiki ke koho ʻia ʻo LOCKPrimiTIves, a hiki i nā mea ʻelua ke hana ʻia e like me ke kiʻi.