Na imewe nke PCB mbadamba, na mmụba ngwa ngwa, a ga-enwe ọtụtụ nnyonye anya nke dị iche na bọọdụ PCB dị ala. Ọzọkwa, na -abawanye ugboro na ihe na -emegiderịta n’etiti miniaturization na ọnụ ala nke bọọdụ PCB, nnyonye anya a ga -adịwanye mgbagwoju anya.

N’ime nyocha n’ezie, anyị nwere ike kwubie na enwere akụkụ anọ nke nnyonye anya, gụnyere mkpọtụ ike ọkọnọ, nnyonye anya eriri nnyefe, njikọta na nnyonye aka elektrọnik (EMI). Site n’ịtụle nsogbu nnyonye anya dị iche iche nke PCB ugboro ugboro yana ijikọ ya na ọrụ, a na-ebute ụzọ dị mma.

Nke mbụ, mkpọtụ ọkọnọ ọkụ

Na sekit ugboro ugboro, mkpọtụ nke ọkọnọ ike nwere mmetụta pụtara ìhè na mgbama mgba ọkụ dị elu. Therefore, the first requirement of the power supply is low noise. Ala dị ọcha dịkwa mkpa dị ka ọkụ eletrik dị ọcha. Maka gịnị? E gosiri njirimara ike na Ọgụgụ 1. N’ụzọ doro anya, ọkụ eletrik nwere ihe mgbochi ụfọdụ, a na -ekesakwa impedance ahụ na ọkụ eletrik niile, yabụ, a ga -etinye mkpọtụ na ọkụ eletrik.

Then we should minimize the impedance of the power supply, so it is best to have a dedicated power supply layer and grounding layer. N’ime imepụta sekit hf, ọ ka mma ịchepụta ike ọkụ dị ka akwa karịa ka bọs n’ọtụtụ oge, ka loop wee nwee ike na -eso ụzọ nke obere impedance.

Tụkwasị na nke ahụ, bọọdụ ike ga -enwerịrị akara mgbaama maka akara niile emepụtara na natara na PCB. Nke a na-ebelata mkpọtụ mgbaama ma si otu a belata mkpọtụ, nke ndị nrụpụta sekit obere oge na-eleghara anya.

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Ọgụgụ 1: Njirimara ike

Enwere ọtụtụ ụzọ iji kpochapụ mkpọtụ ike na imebe PCB:

1. Note the through hole on the board: the through hole requires etched openings on the power supply layer to leave space for the through hole to pass through. Ọ bụrụ na oghere nke ọkọnọ ọkụ eletrik buru oke ibu, ọ ga -emetụta mkpọchi mgbaama, a na -amanye mgbama ka ọ gafere, mpaghara loop na -abawanye, mkpọtụ na -abawanye. At the same time, if several signal lines are clustered near the opening and share the same loop, the common impedance will cause crosstalk. Lee ọgụgụ 2.

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Ọgụgụ 2: Ụzọ a na -ahụkarị maka ịgbanye akara mgbanaka

2. The connection line needs enough ground: each signal needs to have its own proprietary signal loop, and the loop area of the signal and loop is as small as possible, that is to say, the signal and loop should be parallel.

3. Analog na ike dijitalụ ikewapụ: ngwaọrụ ugboro ugboro na-enwekarị mmetụta nke mkpọtụ dijitalụ, yabụ ekwesịrị kewaa ha abụọ, jikọta ọnụ n’ọnụ ụzọ ọkụ, ma ọ bụrụ na mgbama gafere akụkụ analog na dijitalụ nke okwu, enwere ike itinye ya na mgbama gafee loop iji belata mpaghara akaghị. A na-egosi ogologo oge analog-dijitalụ ejiri maka akara mgbama na eserese 3.

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Figure 3: Digital – analog span for signal loop

4. Avoid overlapping of separate power supplies between layers: otherwise circuit noise can easily pass through parasitic capacitive coupling.

5. Isolate sensitive components: such as PLL.

6. Place the power cable: To reduce the signal loop, place the power cable on the edge of the signal line to reduce the noise, as shown in Figure 4.

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Ọgụgụ 4: Debe eriri ọkụ n’akụkụ akara akara

Two, transmission line

Enwere naanị ahịrị nnyefe abụọ enwere ike na PCB:

Nsogbu kasịnụ nke ahịrị eriri na eriri ngwa ndakwa nri bụ echiche. Ịtụgharị uche ga -eweta ọtụtụ nsogbu. Dịka ọmụmaatụ, mgbaama ibu ga -abụ ngosipụta nke akara mbụ na akara mgbagharị, nke ga -abawanye nhịahụ nyocha nyocha. Ntụgharị uche na -ebute mfu nloghachi (mfu nloghachi), nke na -emetụta mgbaama dị ka ndabichi mkpọtụ mkpọtụ:

1. Mgbama ahụ tụgharịrị azụ na isi mgbaama ga -abawanye mkpọtụ nke sistemụ, na -eme ka o siere onye na -anabata ya ike ịmata ụda na mgbaama;

2. Any reflected signal will basically degrade the signal quality and change the shape of the input signal. Generally speaking, the solution is mainly impedance matching (for example, the impedance of the interconnection should very match the impedance of the system), but sometimes the calculation of impedance is more troublesome, you can refer to some transmission line impedance calculation software. The methods of eliminating transmission line interference in PCB design are as follows:

(a) Zere nkwụsị nkwụsị nke ahịrị nnyefe. Ebe nkwụsị ihe nkwụsị bụ ebe nnyefe ahịrị nnyefe, dị ka akụkụ kwụ ọtọ, site na oghere, wdg, kwesịrị izere ruo oke o kwere mee. Ụzọ: Iji zere nkuku kwụ n’ahịrị, ka enwere ike ịga na 45 ° n’akuku ma ọ bụ arc, nnukwu akụkụ nwekwara ike ịbụ; Jiri ole na ole n’ime oghere dị ka o kwere mee, n’ihi na nke ọ bụla site na oghere bụ nkwụsị nkwụsị, dị ka egosiri na FIG. 5; Signals from the outer layer avoid passing through the inner layer and vice versa.

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Figure 5: Method for eliminating transmission line interference

(b) Do not use stake lines. N’ihi na ahịrị ikpo ọ bụla bụ isi iyi nke mkpọtụ. Ọ bụrụ na ahịrị ikpo ahụ dị mkpụmkpụ, enwere ike ijikọ ya na njedebe nke eriri nnyefe; Ọ bụrụ na ahịrị ikpo ahụ dị ogologo, ọ ga -ewere ahịrị nnyefe dị ka isi mmalite ya wee mepụta nnukwu echiche, nke ga -agbagha nsogbu ahụ. Akwadoro ka ị ghara iji ya.

Nke atọ, njikọta

1. Common impedance coupling: it is a common coupling channel, that is, the interference source and the interfered device often share some conductors (such as loop power supply, bus, and common grounding), as shown in Figure 6.

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Ọgụgụ 6: njikọ impedance nkịtị

In this channel, the drop back of the Ic causes a common-mode voltage in the series current loop, affecting the receiver.

2. The field common-mode coupling will cause the radiation source to cause common-mode voltages in the loop formed by the interfered circuit and on the common reference surface.

If the magnetic field is dominant, the value of the common-mode voltage generated in the series ground circuit is Vcm=-(△B/△t)* area (where △B= change in magnetic induction intensity). If it is an electromagnetic field, when its electric field value is known, its induced voltage: Vcm=(L* H *F*E)/48, the formula is suitable for L(m)=150MHz, beyond this limit, the calculation of the maximum induced voltage can be simplified as: Vcm=2* H *E.

3. Differential mode field coupling: refers to the direct radiation by wire pair or circuit board on the lead and its loop induction received. If you get as close to the two wires as possible. Njikọ a na -ebelata nke ukwuu, yabụ enwere ike ịdọgharị wires abụọ ọnụ iji belata ndabichi.

4. Inter-line coupling (crosstalk) can cause unwanted coupling between any line or parallel circuit, which will greatly damage the performance of the system. Its type can be divided into capacitive crosstalk and perceptual crosstalk.

The former is because the parasitic capacitance between the lines makes the noise on the noise source coupled to the noise receiving line through current injection. The latter can be thought of as the coupling of signals between the primary stages of an unwanted parasitic transformer. Ogo nke crosstalk inductive na -adabere na ịdị nso nke loops abụọ, nha mpaghara akaghị, yana nkwụsị nke ibu emetụta.

5. Njikọ eriri ọkụ: Mmetụta eletrọnkị na -emetụta eriri AC ma ọ bụ DC

Nyefee na ngwaọrụ ndị ọzọ.

There are several ways to eliminate crosstalk in PCB design:

1. Ụdị crosstalk abụọ na -abawanye site na mmụba nke impedance ibu, yabụ ahịrị akara ndị nwere mmetụta na nnyonye anya nke crosstalk kpatara kwesịrị ịkwụsị ya nke ọma.

2. Mee ka ogologo dị n’agbata ahịrị mgbama iji belata crosstalk capacitive. Njikwa ala, ịkpa ókè n’etiti eriri ọkụ (dị ka ahịrị mgbama na -arụ ọrụ na ahịrị ala maka ikewapụ, ọkachasị na steeti ima elu n’etiti ahịrị mgbama na ala ruo etiti oge) ma belata ntinye ụzọ.

3. Capacitive crosstalk can also be effectively reduced by inserting a ground wire between adjacent signal lines, which must be connected to the formation every quarter of a wavelength.

4. Maka ikiri ụkwụ nwere ezi uche, ekwesịrị ibelata mpaghara akaghị, ma ọ bụrụ na enyere ya ohere, ekwesịrị iwepụ akaghị.

5. Avoid signal sharing loops.

6. Lezienụ anya na iguzosi ike n’ihe nke ihe mgbaàmà: onye nrụpụta kwesịrị itinye mmechi na usoro ịgbado ọkụ iji dozie iguzosi ike n’ihe. Ndị na -emepụta ihe na -eji usoro a nwere ike ilekwasị anya n’ogo microstrip nke mkpuchi foil ọla iji nweta ezigbo arụmọrụ nke iguzosi ike n’ezi ihe. For systems with dense connectors in the communication structure, the designer can use a PCB as the terminal.

Four, electromagnetic interference

As the speed increases, EMI becomes more and more serious and presents in many aspects (such as electromagnetic interference at interconnects). High-speed devices are particularly sensitive to this and will receive high-speed spurious signals, while low-speed devices will ignore such spurious signals.

Enwere ọtụtụ ụzọ iji kpochapụ nnyonye aka electromagnetic na imebe PCB:

1. Belata loops: loop ọ bụla dabara na antenna, yabụ anyị kwesịrị ibelata ọnụ ọgụgụ loops, mpaghara loops na mmetụta antenna nke loops. Make sure the signal has only one loop path at any two points, avoid artificial loops and use the power layer whenever possible.

2. Filtering: Filtering can be used to reduce EMI on both the power line and the signal line. There are three methods: decoupling capacitor, EMI filter and magnetic element. EMI filter is shown in Figure 7.

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Ọgụgụ 7: Ụdị nzacha

3. The shielding. N’ihi ogologo okwu a gbakwunyere ọtụtụ isiokwu na -echebe isiokwu, enweghịzi nkọwa mmalite.

4. Reduce the speed of high-frequency devices.

5. Mụbaa mbadamba dielectric nke bọọdụ PCB, nke nwere ike igbochi akụkụ ugboro ugboro dị ka eriri nnyefe dị nso na bọọdụ ahụ ka ọ na -enwupụta n’èzí; Increase the thickness of PCB board, minimize the thickness of microstrip line, can prevent electromagnetic line spillover, can also prevent radiation.

At this point, we can conclude that in hf PCB design, we should follow the following principles:

1. Unification and stability of power supply and ground.

2. Eji nlezianya tụlee wires na nkwụsị kwesịrị ekwesị nwere ike iwepu ntụgharị uche.

3. Eji nlezianya lelee wiwi na nkwụsị kwesịrị ekwesị nwere ike ibelata ikuku na -eme ka capacitive na inductive.

4. Achọrọ mkpọchi mkpọtụ iji mezuo ihe EMC chọrọ.