With the increasing speed of PCB signal switching, today’s PCB designers need to understand and control the impedance of PCB traces. Corresponding to the shorter signal transmission times and higher clock rates of modern digital circuits, PCB traces are no longer simple connections, but transmission lines.

Quomodo moderari PCB impedimentum?

In praxi, vestigium impedimenti moderari necesse est cum celeritas marginalis digitalis 1ns vel analogiam frequentiam 300Mhz excedit. Una e clavibus parametris vestigium PCB proprium est eius impedimentum (proportio intentionis ad currentem sicut unda per lineam transmissionis signum percurrit). Proprietas impedimenti fili in circuitu tabulae impressae est index magni ponderis circa tabulam delineandi, praesertim in PCB designatae frequentiae ambitus altae, considerari debet an proprietas impedimenti filum consonet cum charactere impedimenti ab artificio vel signo exigente. This involves two concepts: impedance control and impedance matching. This paper focuses on impedance control and lamination design.

IMMINENTIA imperium

EImpedance Controling, conductor in circuitu tabulae omne genus transmissionis insignem habebit, ut rate tradendi meliori augeatur et frequentiam suam augeat, si linea ipsa ob engraving, tassicula crassitudinis, filum latitudinis et alia diversa, causabit. impedimentum pretii mutationis, signum pravitatis. Impedimentum ergo pretii conductoris in summa celeritate circa tabulam moderari debet intra certum ambitum, notum “impedimentum imperium”.

The impedance of a PCB trace will be determined by its inductive and capacitive inductance, resistance, and conductivity coefficient. The main factors affecting the impedance of PCB wiring are: the width of copper wire, the thickness of copper wire, the dielectric constant of medium, the thickness of medium, the thickness of pad, the path of ground wire, the wiring around the wiring, etc. Impedimentum PCB iugis a 25 ad 120 olim.

In praxi, linea transmissionis PCB plerumque consistit in vestigio, uno vel pluribus stratis referentibus, et in velitationibus materiae. Vestigia et strata formant impedimentum imperium. PCBS saepe multiplex erit, et impedimentum temperantia variis modis construi potest. However, whatever method is used, the impedance value will be determined by its physical structure and the electrical properties of the insulating material:

Latitudo et crassitudo signum vestigium

The height of the core or prefill material on either side of the trace

Configurationis vestigii et laminae

Insulation constants of core and prefilled materials

Lineae transmissionis PCB veniunt in duas formas principales: Microstrip et Stripline.

Microstrip:

Linea microstrip est conductor habena cum plano referente ab una tantum parte, summo et lateribus aeri (vel obductis), supra superficiem velit constans tabula er ambitus, cum potentia copia vel fundatio ut referatur. Ut ostendo subter supter:

Note: In actual PCB manufacturing, the board manufacturer usually coats the surface of the PCB with a layer of green oil, so in actual impedance calculation, the model shown below is usually used for surface microstrip line calculation:

Stripline:

Linea vitta est vitta filum inter duo plana referentia, ut figura infra ostendetur. Constantes dielectrici dielectrici ab H1 et H2 repraesentati possunt esse diversae.

The above two examples are only a typical demonstration of microstrip lines and ribbon lines. There are many kinds of specific microstrip lines and ribbon lines, such as coated microstrip lines, which are related to the specific laminated structure of PCB.

The equations used to calculate the characteristic impedances require complex mathematical calculations, usually using field solving methods, including boundary element analysis, so using the specialized impedance calculation software SI9000, all we need to do is control the parameters of the characteristic impedances:

Dielectric constant Er, wiring width W1, W2 (trapezoid), wiring thickness T and insulation layer thickness H.

W1, W2:

The calculated value must be within the red box. Et ita in.

SI9000 is used to calculate whether the impedance control requirements are met:

First calculate the single-end impedance control of DDR data line:

TOP layer: 0.5oz copper thickness, 5MIL wire width, 3.8mil distance from the reference plane, dielectric constant 4.2. Exemplar elige, in parametris substitue, et calculum incommodum selige, ut figura exhibet:

CoaTing significat coaTingere, et, si nulla vis est, 0 in crassitudine reple, et 1 in dielectric (dielectrica constante) (aera).

Substratum significat stratum substratum, id est, stratum dielectricum, plerumque utens fr-4, crassitudo ratione impedimenti programmatis calculi, dielectric 4.2 constant (frequentia minus quam 1GHz).

Click on Weight (oz) to set the thickness of the copper layer, which determines the thickness of the cable.

9. Prepreg/Core conceptus iacuit velit

PP (Prepreg) est quaedam materia dielectrica ex fibra vitrea et resina epoxy composita. TYPE mediae PP revera est Core, sed duo latera eius claua cuprea teguntur, PP non est. Cum multilayri tabulas faciunt, nucleus et PP simul uti solent, et PP chirographum inter nucleum et nucleum adhibetur.

10. Rebus egens operam in PCB laminationis design

(1) Warpage problem

Iacurationis PCB ratio debet esse symmetrica, id est, crassitudo mediae tabulae et aenei cuiuslibet lavacri aequalis esse debet. Exempli gratia sumatur sex stratorum, crassitudo mediae potentiae summae GND et solum mediae crassitudini aeris consonans, et medii GND-L2 et L3 crassitudini aeris congruere debet. Non hoc detorto laminating.

(2) Insigne iacuit arcte coniungi cum plano adiacentibus referentiis (id est, mediae crassitudinis inter iacuit signum et stratum aeris adiacentem bitumine perexiguum esse debet); Virtus aenea conpositio et tritus aeneus arcte iungendus est.

(3) In casu praealtae celeritatis extra stratis signum tabulatum segregare addi potest, sed commendatur ne multiplicem vim stratorum segregare, quae strepitum supervacuum impedire possit.

(4) Distinctio strata designationis typicae laminatis in sequenti tabula ostenditur:

(5.) Principia generalia ordinis accumsan;

Infra superficiem component (in secundo tabulato) est planum humum, quod fabrica protegens stratum praebet et planum referat ad summum iacum wiring;

Omnes stratae signo adiacent plano terrae, quantum fieri potest.

Vitare adiacentiam directam inter duas laminis insignes, quantum fieri potest;

Summa potentiarum copia debet esse quam maxime vicina;

Symmetria structurae laminae habenda est ratio.

For the layer layout of the motherboard, it is difficult for the existing motherboard to control the parallel long-distance wiring, and the working frequency of the board level is above 50MHZ

(Nam condiciones infra 50MHZ, ad eam referri et apte relaxare placet), principium layout suggeritur:

Superficies componentis et superficies glutino sunt integrae terrae planae (scutum);

Stratum wiring parallelum nulli adjacentium;

Omnes stratae signo adiacent plano terrae, quantum fieri potest.

Signum clavis formationi adjacet et zonam segmentationis non transit.