Me ka ʻole o ka impedance control, e hoʻokau ʻia ka noʻonoʻo ʻana i ka hōʻailona a me ka distortion, e hopena ai i ka holomua o ka hoʻolālā. ʻO nā hōʻailona maʻamau, e like me ke kaʻa ʻo PCI, pahi PCI-E, USB, Ethernet, hoʻomanaʻo DDR, hōʻailona LVDS, a pēlā aku, pono ka mālama impedance āpau. Impedance control ultimately needs to be realized through PCB design, which also puts forward higher requirements for PCB board technology. After communication with PCB factory and combined with the use of EDA software, the impedance of wiring is controlled according to the requirements of signal integrity.

Hiki ke helu ʻia i nā ʻano uila e loaʻa ai ka waiwai impedance like.

Nā laina microstrip

Aia i loko o kahi kaula uea me ka mokulele honua a me ka dielectric i waenakonu. Inā kū mau ka dielectric, ka laulā o ka laina, a me kona mamao mai ka mokulele honua kaohi, a laila hiki ke kaohi ʻia kona ʻano impedance, a aia ka pololei ma waena o 5%.

Impedance control based on PCB design

Laina

ʻO kahi laina lipine kahi kaula keleawe i waenakonu o ka dielectric ma waena o nā mokulele alakaʻi ʻelua. Inā ka mānoanoa a me ka laulā o ka laina, ka dielectric mau o ka waena, a me ka mamao ma waena o nā papa honua o nā papa ʻelua e hiki ke kāohi ʻia, hiki ke kaʻi ʻia ka hiʻohiʻona impedance o ka laina, a aia ka pololei ma 10%.

Impedance control based on PCB design

ʻO ke ʻano o ka papa multi-layer:

I mea e kaohi pono ai i ka impedance PCB, pono e hoʻomaopopo i ke ʻano o PCB:

ʻO ka mea maʻamau a mākou i kapa aku ai he papa multilayer i hana ʻia me ka pā nui a me ka pepa laminated semi-solidified pū kekahi me kekahi. ʻO ka papa Core he paʻakikī, mānoanoa kikoʻī, ʻelua pā keleawe berena, ʻo ia ka mea maʻa o ka papa pai. A ʻo ka ʻāpana semi-cured ka mea i kapa ʻia he infiltration layer, hoʻokani i ke ʻano o ka hoʻopaʻa ʻana i ka pā nui, ʻoiai aia kahi mānoanoa mua, akā i ke kaʻina o ke kaomi ʻana i kona mānoanoa e loli kekahi mau loli.

ʻO ka maʻa mau ʻo nā papa dielectric ʻelua o ka multilayer i pulu ʻia, a hoʻohana ʻia nā papa keleawe keleawe ma waho o kēia mau papa ʻelua e like me ka pepa keleawe waho. ʻO ke kikoʻī o ka mānoanoa o ka pepa keleawe o waho a me ka foil keleawe o loko he 0.5oz, 1OZ, 2OZ (ʻo 1OZ e pili ana i 35um a i ʻole 1.4mil), akā ma hope o ke kaʻina o ka mālama ʻana i ka papa, e hoʻonui ka mānoanoa hope loa o nā pepa keleawe waho e pili ana. 1OZ. ʻO ka pepa keleawe o loko ka uhi keleawe ma nā ʻaoʻao ʻelua o ka pā nui. ʻOkoʻa iki ka mānoanoa hope loa i ka mānoanoa kumu, akā hoʻemi ʻia ia e kekahi mau um ma muli o ka hoʻopaʻa ʻana.

ʻO ka papa waho loa o ka papa multilayer ka pale kuʻihao wili, ʻo ia ka mea a mākou e ʻōlelo pinepine ai he “aila ʻōmaʻomaʻo”, ʻoiaʻiʻo, hiki ke melemele a i ʻole nā ​​kala ʻē aʻe. ʻAʻole maʻalahi ka mānoanoa o ka papa pale pale solder e hoʻoholo pololei. ʻO ka wahi me ka ʻole o ka pepa keleawe ma luna o ka papa he mānoanoa iki ma mua o ka wahi me ka pepa keleawe, akā no ka nele o ka mānoanoa o ka pepa keleawe, no laila ʻoi aku ke koʻikoʻi o ka pepa keleawe, ke pā mākou i ka papa paʻi i pai ʻia me ko mākou mau manamana lima.

Ke hana ʻia kahi mānoanoa o ka papa paʻi, ma kekahi lima, koi ʻia nā koho kūpono o nā mea kikoʻī, ma ka ʻaoʻao ʻē aʻe, e ʻoi aku ka liʻiliʻi o ka mānoanoa hope loa o ka pepa semi-cured ma mua o ka mānoanoa mua. ʻO ka aʻe aʻe kahi ʻano lamineka 6-ʻāpana maʻamau:

Impedance control based on PCB design

Nā palena PCB:

Loaʻa nā ʻokoʻa iki o nā mea kanu PCB i nā palena PCB. Ma o ke kamaʻilio pū ʻana me ke kākoʻo loea o ka mea kanu papa kaapuni, loaʻa iā mākou kekahi ʻikepili parameter o ka mea kanu:

ʻO ka pepa kila keleawe:

ʻEkolu mānoanoa o ka pepa keleawe e hiki ke hoʻohana ʻia: 12um, 18um a me 35um. ʻO ka mānoanoa hope loa ma hope o ka pau ʻana ma kahi o 44um, 50um a me 67um.

Pā nui: S1141A, FR-4 maʻamau, hoʻohana mau ʻia nā pā keleawe berena ʻelua. Hiki ke hoʻoholo i nā kikoʻī koho ma ke kāhea ʻana i ka mea hana.

Pākuʻi semi-cured:

Nā kikoʻī (mānoanoa kumu) 7628 (0.185mm), 2116 (0.105mm), 1080 (0.075mm), 3313 (0.095mm). ʻO ka mānoanoa maoli ma hope o ke kaomi ʻana ma kahi o 10-15um ka liʻiliʻi ma mua o ka waiwai kumu. Hiki ke hoʻohana ʻia i kahi kiʻekiʻena o 3 mau papa semi-cured no ka papa infiltration like, a ʻaʻole hiki ke like ka mānoanoa o 3 papa semi-cured, ma kahi o hoʻokahi hapalua i hoʻōla ʻia e hoʻohana ʻia nā papa, akā pono e hoʻohana kekahi mau mea hana i ʻelua mau mea. . Inā ʻaʻole lawa ka mānoanoa o ka ʻāpana semi-cured, hiki ke hoʻopaʻa ʻia ka pepa keleawe ma nā ʻaoʻao ʻelua o ka pā nui, a laila hiki ke hoʻopili ʻia ka ʻāpana semi-cured ma nā ʻaoʻao ʻelua, i hiki ai i kahi papa infiltration mānoanoa ke hoʻopaʻa ʻia. loaʻa.

Māhele ʻaoʻao:

E noʻonoʻo mākou ʻo ka ʻāpana keʻa o ka uea he huinahā lōʻihi, akā he trapezoid maoli ia. Lawe i ka papa TOP ma ke ʻano he laʻana, ke lilo ka mānoanoa o ka pepa kila keleawe i ka 1OZ, ʻo ka palena o luna o trapezoid ʻo 1MIL ka pōkole ma mua o ka lihi lalo o lalo. ʻO kahi laʻana, inā ʻo 5MIL ka laulā o ka laina, a laila ʻo ka ʻaoʻao luna a me lalo e pili ana i 4MIL a ʻo ka ʻaoʻao lalo a me lalo e pili ana iā 5MIL. ʻO ka ʻokoʻa ma waena a ma nā lihi o lalo e pili ana i ka mānoanoa o ke keleawe. Hōʻike ka papa aʻe i ka pilina ma waena o luna a me lalo o trapezoid ma lalo o nā ʻano like ʻole.

Impedance control based on PCB design

ʻAeʻae: ʻO ka ʻae ʻana o nā pale semi-cured e pili ana i ka mānoanoa. Hōʻike ka papa aʻe i ka mānoanoa a me ka palena o ka ʻae ʻana o nā ʻano like ʻole o nā pale semi-cured.

Impedance control based on PCB design

Pili ka paʻa dielectric o ka pā i nā mea kēpau i hoʻohana ʻia. ʻO ka hoʻomau dielectric o ka pā FR4 he 4.2 – 4.7, a e emi me ka hoʻonui ʻana o ke alapine.

ʻO ke kumu pohō dielectric: nā mea dielectric ma lalo o ka hana o ka alternating kahua uila, ma muli o ka wela a me ka hoʻohana ʻana o ka ikehu i kapa ʻia he dielectric loss, i hōʻike pinepine ʻia e ka mea pohō dielectric Tan δ. ʻO ka waiwai maʻamau no S1141A ka 0.015.

Ka liʻiliʻi o ka laina laina a me ka spacing line e hōʻoia i ka mīkini ʻana: 4mil / 4mil.

Hoʻokomo i ka pono hana helu helu Impedance:

Ke hoʻomaopopo mākou i ke ʻano o ka papa multilayer a haku i nā palena i makemake ʻia, hiki iā mākou ke helu i ka impedance ma o ka polokalamu EDA. Hiki iā ʻoe ke hoʻohana iā Allegro e hana i kēia, akā paipai wau iā Polar SI9000, kahi mea hana maikaʻi no ka helu ʻana i ka impedance ʻano a hoʻohana ʻia e nā hale hana PCB he nui.

Ke helu nei i ka impedance ʻano o ka hōʻailona o loko o ka laina ʻokoʻa a me ka laina laina hoʻokahi, e ʻike ʻoe i kahi ʻokoʻa iki ma waena o Polar SI9000 a me Allegro ma muli o kekahi mau kikoʻī, e like me ke ʻano o ka ʻāpana keʻa o ka uea. Eia nō naʻe, inā e helu ia i ka impedance ʻano o ka hōʻailona Surface, ke ʻōlelo nei wau e koho ʻoe i ke kope i uhi ʻia ma kahi o ka hiʻohiʻona Surface, no ka mea ʻo ia mau hiʻohiʻona e noʻonoʻo i ka noho ʻana o ka papa pale pale solder, no laila ʻoi aku ka pololei o nā hopena. ʻO ka mea aʻe kahi kiʻi screenshot o ka impedance laina ʻokoʻa pae i helu ʻia me Polar SI9000 e noʻonoʻo nei i ka papa pale pale solder:

ʻOiai ʻaʻole maʻalahi ka mānoanoa o ka pale solder resist, hiki ke hoʻohana ʻia i kahi ala kokoke, e like me ka ʻōlelo a ka mea hana papa: e unuhi i kahi waiwai kikoʻī mai ka helu hoʻohālikelike Surface. Paipai ʻia ka hoʻemi ʻia o ka impedance ʻokoʻa ma kahi o 8 ohm a ʻo ka impedance hoʻokahi hopena e lawe ʻia i 2 ohm.

Nā koi PCB ʻokoʻa no ka uea ʻana

(1) E hoʻoholo i ke ʻano uila, nā palena a me ka helu impedance. Aia he ʻelua ʻano ʻokoʻa ʻokoʻa no ke kaʻina laina: ʻo ka ʻokoʻa ʻokoʻa laina laina microstrip waho a me ka ʻokoʻa laina laina ʻaoʻao o loko. Hiki ke helu ʻia ka imppedance e ka polokalamu hoʻohelu impedance pili (e like me POLAR-SI9000) a i ʻole ka impedance calculation formula ma o ka hoʻonohonoho pono parameter.

(2) Nā lālani isometric like. E hoʻoholo i ka laulā a me ka spacing, a hāhai pono i ka laulā laina i helu ʻia a me ka spacing i ka wā e hele ana. ʻO ka hoʻokaʻawale ma waena o nā laina ʻelua e noho mau i ka hoʻololi ʻole, ʻo ia hoʻi, e hoʻomau i ka like. ʻElua ala o ka parallelism: ʻo kekahi ke hele nei nā laina ʻelua i ka ʻaoʻao ʻaoʻao a ʻaoʻao, a ʻo ka lua ke hele nei nā laina ʻelua i ka papa ma lalo o ka papa. E hoʻāʻo maʻamau e hōʻole i ka hoʻohana ʻana i ka hōʻailona ʻokoʻa ma waena o nā papa, ʻo ia hoʻi no ka hana maoli ʻana o PCB i ke kaʻina hana, ma muli o ka cascading laminated alignment ʻoi aku ka haʻahaʻa ma mua o ka mea i hāʻawi ʻia ma waena o ka kikoʻī a me ka hana o ka laminated dielectric loss, ʻaʻole hiki ke hōʻoia i ka hoʻokaʻawale ʻana i ka laina laina i ka mānoanoa o ka dilayer uila, e hana i ka ʻokoʻa ma waena o nā papa o ka ʻokoʻa o ka hoʻololi impedance. Paipai ʻia e hoʻohana i ka ʻokoʻa ma waena o ka papa like e like me ka hiki.