Electricitas statica e corpore humano, ambitu et etiam intra machinis electronicis varia damna praecisionis semiconductoris astularum causare potest, ut tenuem stratum intra partes velit penetrans; Damnum ad portas MOSFET et CMOS componendas; Trigger lock in CMOS device; Short-circuit reverse bias PN junction; Brevis circuitus positivus inclinatio PN coniunctas; Filum pugillum vel aluminium intra machinam activam confla. In order to eliminate the interference and damage of electrostatic discharge (ESD) to electronic equipment, it is necessary to take a variety of technical measures to prevent.

in PCB tabula consilio, resistentia PCB ESD perfici potest per stratum, propriam institutionem et extensionem. In consilio processus, plurimae mutationes designationis limitari possunt ad componentes vel addendo vel tollendo per praedictionem. PCB extensionem componendo et wiring bene impediri potest ESD. Here are some common precautions.

How to realize ESD resistance design of PCB

1. Use multi-layer PCB as far as possible. Compared with double-sided PCB, the ground plane and power plane, as well as the close spacing between signal wire and ground wire can reduce the common-mode impedance and inductive coupling, and make it reach 1/10 to 1/100 of the double-sided PCB. Try to place each signal layer close to a power or ground layer. For high-density PCBS with components on both the top and bottom surfaces, very short connections, and lots of ground filling, consider using inner lines.

2. Pro duplici postesque PCB potestate arcte intertexta et eget terra adhibenda est. Potestas funiculus iuxta terram est et quam maxime inter lineas verticales et horizontales coniungi debet vel zonas replere. The grid size of one side shall be less than or equal to 60mm, or less than 13mm if possible.

3. Perficite, ut unumquodque spatium quam maxime compactum sit.

4. Omnes connexiones quam maxime omitte.

5. Si fieri potest, potestatem funiculi e centro card auferendi ab areis vulnerabilibus ad damnum ESD direct.

6, in omnibus PCB stratis infra iungentem e casu ducentibus (facile ESD directe percussum), locum latum chassis vel polygonum terram repletam, et cum foraminibus inter 13mm circiter interiectis coniunge.

7. Place mounting holes on the edge of the card, and the top and bottom pads of open flux are connected to the ground of the chassis around the mounting holes.

8, PCB assembly, do not apply any solder on the top or bottom pad. Use screws with built-in washers to provide tight contact between PCB and metal chassis/shield or support on ground surface.

9, in utroque tabulato inter gb et terram ambitum, ad eandem “zonam solitariam”; Si fieri potest, servat spatium ad 0.64mm.

10, in the top and bottom of the card near the installation hole position, every 100mm along the chassis ground and circuit ground with 1.27mm wide line together. Adjacent to these connection points, a pad or mounting hole for installation is placed between the chassis ground and the circuit ground. These ground connections can be cut with a blade to remain open, or jump with magnetic beads/high frequency capacitors.

11, if the circuit board will not be put into the metal box or shielding device, the top and bottom of the circuit board chassis ground wire can not be coated with solder resistance, so that they can be used as ESD arc put electrode.

12. Set a ring around the circuit in the following manner:

(1) In addition to the edge connector and chassis, the entire periphery of the ring access.

(2) Ut latitudo omnium stratorum maior sit quam 2.5mm.

(3) Foramina connexa singulis anulo 13 mm.

(4) Connectunt annales et communes multi- strati ambitus.

(5) For double panels installed in metal cases or shielding devices, the ring ground shall be connected to the common ground of the circuit. Circuitus obtentu duplicatus cum anuli humo coniungi debet, anulus humus fluxu obduci non debet, ita ut anulus humus in virga ESD emissa agere possit, saltem 0.5mm latum hiatum in anuli loco (all. stratis), ut magna ansa evitari possit. Signum wiring ab anulo terra non minus quam 0.5mm abesse debet.

In area quae directe ab ESD feriri potest, filum humi iuxta lineam singulae signo positae debet.

14. The I/O circuit should be as close to the corresponding connector as possible.

15. The circuit susceptible to ESD should be placed near the center of the circuit, so that other circuits can provide a certain shielding effect for them.

16, plerumque in serie resistoris et globuli magnetici in fine accepto, et pro his funem aurigarum ESD vulnerabilium, etiam considerare potest seriem resistoris vel globuli magnetici in fine rectoris collocandi.

17. Protector transiens in fine accipientis collocari solet. filis brevibus crassis utere (minus quam 5x latitudo, potius minus quam 3x latitudo) ad gb conectere pavimentum. Signum et humus lineae a iungente directo coniungi debent cum protectore transeunti ante reliquum ambitum coniungi posse.

18. Pone capacitorem colum ad iungentem vel intra 25mm circuitus recipientis.

(1) Utere filum breve et crassum ad connectendum gb seu ambitum recipiendum (longitudo minus quam 5 temporibus latitudo, potius minus quam 3 temporibus latitudo).

(2) Signum lineae et filum humus primum ad capacitorem connexum et deinde ad recipiendum ambitum connexum.

19. Fac acies signum quam brevissime.

20. Cum longitudo funerum signorum sit maior quam 300mm, funis fundi parallelus ponatur.

21. Perficite, ut ansa inter lineam insignem et ansam debitam quam minimam sit. Pro longis lineis signo, positio lineae signi et lineae fundi debet singulae paucae centimeters mutari ad ansam area reducere.

22. Signa mina a centro retis in plures circulos recipiendos.

23. Ensure that the loop area between the power supply and the ground is as small as possible. Place a high frequency capacitor near each power pin of the IC chip.

24. Pone altam frequentiam praeter capacitatem intra 80mm cuiusque connectoris.

25. Where possible, fill the unused areas with land, connecting all layers of fill at 60mm intervals.

26. Fac terram coniunctam duobus finibus oppositis cuiusvis amplae terrae aream replere (proxime maior quam 25mm*6mm).

27. Cum longitudo orificium de potentia copia vel terra planum 8mm excedit, duo latera orimenti cum linea angusta coniunge.

28. Reset linea, interrumpere signum lineae vel extremae felis signo lineae non debet poni circa marginem PCB.

29. Coniunge ascensiones communi ambitu foraminibus, vel eas recludet.

(1) Cum bracket metallica adhibenda est cum scuto metallico fabrica vel gb, nulla ohm resistentia adhibenda est ad nexum percipere.

(2) Determinare foraminis escendere magnitudinem ad certam institutionem metalli vel plastici subsidii consequendam, in summo et infimo foramine adscendente utatur magna caudex, imo codex uti non potest resistentia fluxa, et curet ut fundum. codex non utitur processu elatum glutino ad glutino.

30. Funes datos muniti et ancoras nudati in parallela disponi non possunt.

Praecipua ratio habenda est ad filum retexere, lineas signo interrumpere et regere.

(1) Summus frequentia eliquatio adhibenda est.

(2) Absiste ab input et output circuitus.

(3) Abstinere ab ora tabulae circuitus.

32, PCB in chassis inseri debet, ne in positione aperiendi vel internos articulos instituat.

Attende ad filum signum lineae sub magnetica capita, inter pads et ut magneticam capita attingere. Quaedam capita electricitatem satis bene agunt et vias inopinatas conductivas producunt.

Si casus vel motherboard ut plures tabulas ambitus instituat, maxime sensitivum sit ad electricitatis statice circa tabulam in medio.