In the design of vias in high-speed PCBs, the following points need to be paid attention to

In high-speed HDI PCB design, via design is an important factor. It consists of a hole, a pad area around the hole, and an isolation area of ​​the POWER layer, which are usually divided into three types: blind holes, buried holes and through holes. In the PCB design process, through the analysis of the parasitic capacitance and parasitic inductance of the vias, some precautions in the design of high-speed PCB vias are summarized.


At present, high-speed PCB design is widely used in communications, computers, graphics and image processing and other fields. All high-tech value-added electronic product designs are pursuing features such as low power consumption, low electromagnetic radiation, high reliability, miniaturization, and light weight. In order to achieve the above goals, via design is an important factor in high-speed PCB design.

1. Via
Via is an important factor in multi-layer PCB design. A via is mainly composed of three parts, one is the hole; the other is the pad area around the hole; and the third is the isolation area of ​​the POWER layer. The process of the via hole is to plate a layer of metal on the cylindrical surface of the hole wall of the via hole by chemical deposition to connect the copper foil that needs to be connected to the middle layers, and the upper and lower sides of the via hole are made into ordinary pads The shape can be directly connected with the lines on the upper and lower sides, or not connected. Vias can play the role of electrical connection, fixing or positioning devices.

Vias are generally divided into three categories: blind holes, buried holes and through holes.

Blind holes are located on the top and bottom surfaces of the printed circuit board and have a certain depth. They are used to connect the surface line and the underlying inner line. The depth of the hole and the diameter of the hole usually do not exceed a certain ratio.

Buried hole refers to the connection hole located in the inner layer of the printed circuit board, which does not extend to the surface of the circuit board.

Blind vias and buried vias are both located in the inner layer of the circuit board, which is completed by a through-hole forming process before lamination, and several inner layers may be overlapped during the formation of vias.

Through holes, which pass through the entire circuit board, can be used for internal interconnection or as a component’s installation positioning hole. Since through holes are easier to implement in process and lower cost, generally printed circuit boards use through holes.

2. Parasitic capacitance of vias
The via itself has parasitic capacitance to ground. If the diameter of the isolation hole on the ground layer of the via is D2, the diameter of the via pad is D1, the thickness of the PCB is T, and the dielectric constant of the board substrate is ε, then The parasitic capacitance of the via is similar to:

C =1.41εTD1/(D2-D1)

The main effect of the parasitic capacitance of the via hole on the circuit is to extend the rise time of the signal and reduce the speed of the circuit. The smaller the capacitance value, the smaller the effect.

3. Parasitic inductance of vias
The via itself has parasitic inductance. In the design of high-speed digital circuits, the harm caused by the parasitic inductance of the via is often greater than the influence of the parasitic capacitance. The parasitic series inductance of the via will weaken the function of the bypass capacitor and weaken the filtering effect of the entire power system. If L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center hole, the parasitic inductance of the via is similar to:

L=5.08h[ln(4h/d) 1]

It can be seen from the formula that the diameter of the via has a small influence on the inductance, and the length of the via has the greatest influence on the inductance.

4. Non-through via technology
Non-through vias include blind vias and buried vias.

In the non-through via technology, the application of blind vias and buried vias can greatly reduce the size and quality of the PCB, reduce the number of layers, improve electromagnetic compatibility, increase the characteristics of electronic products, reduce costs, and also make the design work more Simple and fast. In traditional PCB design and processing, through holes can bring many problems. First, they occupy a large amount of effective space, and secondly, a large number of through holes are densely packed in one place, which also creates a huge obstacle to the inner layer wiring of the multilayer PCB. These through holes occupy the space required for the wiring, and they intensively pass through the power supply and the ground. The surface of the wire layer will also destroy the impedance characteristics of the power ground wire layer and make the power ground wire layer ineffective. And the conventional mechanical method of drilling will be 20 times the workload of non-through hole technology.

In PCB design, although the size of pads and vias have gradually decreased, if the thickness of the board layer is not proportionally reduced, the aspect ratio of the through hole will increase, and the increase of the aspect ratio of the through hole will reduce the reliability. With the maturity of advanced laser drilling technology and plasma dry etching technology, it is possible to apply non-penetrating small blind holes and small buried holes. If the diameter of these non-penetrating vias is 0.3mm, the parasitic parameters will be About 1/10 of the original conventional hole, which improves the reliability of the PCB.

Due to the non-through via technology, there are few large vias on the PCB, which can provide more space for traces. The remaining space can be used for large-area shielding purposes to improve EMI/RFI performance. At the same time, more remaining space can also be used for the inner layer to partially shield the device and key network cables, so that it has the best electrical performance. The use of non-through vias makes it easier to fan out the device pins, making it easy to route high-density pin devices (such as BGA packaged devices), shortening the wiring length, and meeting the timing requirements of high-speed circuits.

5. Via selection in ordinary PCB
In ordinary PCB design, the parasitic capacitance and parasitic inductance of the via have little effect on the PCB design. For the 1-4 layer PCB design, 0.36mm/0.61mm/1.02mm (drilled hole/pad/POWER isolation area is generally selected) ) Vias are better. For signal lines with special requirements (such as power lines, ground lines, clock lines, etc.), 0.41mm/0.81mm/1.32mm vias can be used, or vias of other sizes can be selected according to the actual situation.

6. Via design in high-speed PCB
Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to the circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

(1) Choose a reasonable via size. For multi-layer general-density PCB design, it is better to use 0.25mm/0.51mm/0.91mm (drilled holes/pads/POWER isolation area) vias; for some high-density PCBs, 0.20mm/0.46 can also be used mm/0.86mm vias, you can also try non-through vias; for power or ground vias, you can consider using a larger size to reduce impedance;

(2) The larger the POWER isolation area, the better, considering the via density on the PCB, generally D1=D2 0.41;

(3) Try not to change the layers of the signal traces on the PCB, which means to minimize vias;

(4) The use of a thinner PCB is conducive to reducing the two parasitic parameters of the via;

(5) The power and ground pins should be made via holes nearby. The shorter the lead between the via hole and the pin, the better, because they will increase the inductance. At the same time, the power and ground leads should be as thick as possible to reduce impedance;

(6) Place some grounding vias near the vias of the signal layer to provide a short-distance loop for the signal.

Of course, specific issues need to be analyzed in detail when designing. Considering both cost and signal quality comprehensively, in high-speed PCB design, designers always hope that the smaller the via hole is, the better, so that more wiring space can be left on the board. In addition, the smaller the via hole, its own The smaller the parasitic capacitance, the more suitable for high-speed circuits. In high-density PCB design, the use of non-through vias and the reduction in the size of vias have also brought about an increase in cost, and the size of vias cannot be reduced indefinitely. It is affected by PCB manufacturers’ drilling and electroplating processes. Technical limitations should be given balanced consideration in the via design of high-speed PCBs.