How to avoid transmission line effect in high speed PCB design?

How to avoid transmission line effect in high-speed PCB design

1. Methods to suppress electromagnetic interference

A good solution to the signal integrity problem will improve the electromagnetic compatibility (EMC) of the PCB board. One of the most important is to ensure that the PCB board has good grounding. A signal layer with a ground layer is a very effective method for complex design. In addition, minimizing the signal density of the outermost layer of the circuit board is also a good way to reduce electromagnetic radiation. This method can be achieved by using the “surface area” technology “build-up” PCB design. The surface area layer is achieved by adding a combination of thin insulation layers and micropores used to penetrate these layers on a general-process PCB. The resistance and capacitance can be buried beneath the surface, and the linear density per unit area is nearly doubled, thus reducing the volume of the PCB. The reduction of PCB area has a huge impact on the topology of routing, which means that the current loop is reduced, the length of branch routing is reduced, and the electromagnetic radiation is approximately proportional to the area of the current loop; At the same time, the small size characteristics mean that high-density pin packages can be used, which in turn reduces the length of the wire, thus reducing the current loop and improving emc characteristics.

2. Strictly control the cable lengths of key network cables

If the design has a high speed jump edge, the transmission line effect on the PCB must be considered. The high clock rate fast integrated circuit chips commonly used today are even more problematic. There are some basic principles to solve this problem: if CMOS or TTL circuits are used for design, the operating frequency is less than 10MHz, and the wiring length should not be greater than 7 inches. If the operating frequency is 50MHz, the cable length should not be greater than 1.5 inches. Wiring length should be 1 inch if operating frequency reaches or exceeds 75MHz. The maximum wiring length for GaAs chips should be 0.3 inches. If this is exceeded, there is a transmission line problem.

3. Properly plan the topology of cabling

Another way to solve the transmission line effect is to choose the correct routing path and terminal topology. The cabling topology refers to the cabling sequence and structure of a network cable. When high-speed logic devices are used, the signal with rapidly changing edges will be distorted by the branches of the signal trunk unless the branch length is kept very short. In general, PCB routing adopts two basic topologies, namely Daisy Chain routing and Star distribution.

For daisy-chain wiring, wiring starts at the driver end and reaches each receiving end in turn. If a series resistor is used to change the signal characteristics, the position of the series resistor should be close to the driving end. Daisy chain cabling is the best in controlling the high harmonic interference of cabling. However, this kind of wiring has the lowest transmission rate and is not easy to pass 100%. In the actual design, we want to make the branch length in Daisy chain wiring as short as possible, and the safe length value should be: Stub Delay < = Trt * 0.1.

For example, branch ends in high-speed TTL circuits should be less than 1.5 inches long. This topology takes up less wiring space and can be terminated by a single resistor matching. However, this wiring structure makes the signal receiving at different signal receiver is not synchronous.

The star topology can effectively avoid the problem of clock signal synchronization, but it is very difficult to finish the wiring manually on the PCB with high density. Using automatic cabler is the best way to complete star cabling. A terminal resistor is required on each branch. The value of the terminal resistance should match the characteristic impedance of the wire. This can be done manually or through CAD tools to calculate the characteristic impedance values and terminal matching resistance values.

While simple terminal resistors are used in the two examples above, a more complex matching terminal is optional in practice. The first option is the RC match terminal. RC matching terminals can reduce power consumption, but can only be used when the signal operation is relatively stable. This method is most suitable for clock line signal matching processing. The disadvantage is that the capacitance in the RC matching terminal may affect the shape and propagation speed of the signal.

The series resistor matching terminal incurs no additional power consumption, but slows down signal transmission. This approach is used in bus-driven circuits where time delays are not significant. The series resistor matching terminal also has the advantage of reducing the number of devices used on the board and the density of connections.

The final method is to separate the matching terminal, in which the matching element needs to be placed near the receiving end. Its advantage is that it will not pull down the signal, and can be very good to avoid noise. Typically used for TTL input signals (ACT, HCT, FAST).

In addition, the package type and installation type of the terminal matching resistor must be considered. SMD surface mount resistors generally have lower inductance than through-hole components, so SMD package components are preferred. There are also two installation modes for ordinary straight plug resistors: vertical and horizontal.

In vertical mounting mode, the resistance has a short mounting pin, which reduces the thermal resistance between the resistance and the circuit board and makes the resistance heat more easily emitted into the air. But a longer vertical installation will increase the inductance of the resistor. Horizontal installation has lower inductance due to lower installation. However, the overheated resistance will drift, and in the worst case, the resistance will become open, resulting in PCB wiring termination matching failure, becoming a potential failure factor.

4. Other applicable technologies

In order to reduce transient voltage overshoot on IC power supply, decoupling capacitor should be added to IC chip. This effectively removes the impact of burrs on the power supply and reduces the radiation from the power loop on the printed board.

The burr smoothing effect is best when the decoupling capacitor is connected directly to the power supply leg of the integrated circuit rather than to the power supply layer. This is why some devices have decoupling capacitors in their sockets, while others require the distance between the decoupling capacitor and the device to be small enough.

Any high speed and high power consumption devices should be placed together as far as possible to reduce transient overshoot of power supply voltage.

Without a power layer, long power lines form a loop between the signal and the loop, serving as a source of radiation and an inductive circuit.

Cabling forming a loop that does not pass through the same network cable or other cabling is called open loop. If the loop passes through the same network cable, other routes form a closed loop. In both cases, the antenna effect (line antenna and ring antenna) can occur.