Bi o ṣe le yago fun ipa laini gbigbe ni PCB iyara to gaju design

1. Awọn ọna lati dinku kikọlu itanna

Ojutu ti o dara si iṣoro iduroṣinṣin ifihan yoo mu ibaramu itanna (EMC) ti igbimọ PCB dara. Ọkan ninu pataki julọ ni lati rii daju pe igbimọ PCB ni ilẹ ti o dara. Ipele ifihan pẹlu fẹlẹfẹlẹ ilẹ jẹ ọna ti o munadoko pupọ fun apẹrẹ eka. Ni afikun, idinku iwuwo ifihan ti fẹlẹfẹlẹ ti ita ti igbimọ Circuit tun jẹ ọna ti o dara lati dinku itankalẹ itanna. Ọna yii le ṣaṣeyọri nipa lilo imọ-ẹrọ “agbegbe dada” imọ-ẹrọ “kọ-soke” apẹrẹ PCB. Ipele agbegbe agbegbe jẹ aṣeyọri nipa fifi apapọ kan ti awọn fẹlẹfẹlẹ idabobo tinrin ati awọn micropores ti a lo lati wọ inu awọn fẹlẹfẹlẹ yii lori PCB ilana gbogbogbo. Iduroṣinṣin ati kapasito ni a le sin labẹ ilẹ, ati iwuwo laini fun agbegbe ẹyọkan ti fẹrẹ ilọpo meji, nitorinaa dinku iwọn didun ti PCB. Idinku ti agbegbe PCB ni ipa nla lori topology ti afisona, eyiti o tumọ si pe lupu lọwọlọwọ ti dinku, gigun ti ipa ọna ti dinku, ati itankalẹ itanna jẹ isunmọ deede si agbegbe ti lupu lọwọlọwọ; At the same time, the small size characteristics mean that high-density pin packages can be used, which in turn reduces the length of the wire, thus reducing the current loop and improving emc characteristics.

2. Strictly control the cable lengths of key network cables

If the design has a high speed jump edge, the transmission line effect on the PCB must be considered. Oṣuwọn aago giga ti o yara awọn eerun Circuit iṣọpọ ti a lo nigbagbogbo jẹ paapaa iṣoro diẹ sii. Diẹ ninu awọn ipilẹ ipilẹ wa lati yanju iṣoro yii: ti a ba lo awọn iyika CMOS tabi TTL fun apẹrẹ, igbohunsafẹfẹ ṣiṣiṣẹ ko kere ju 10MHz, ati ipari wiwọn ko yẹ ki o tobi ju awọn inṣi 7 lọ. If the operating frequency is 50MHz, the cable length should not be greater than 1.5 inches. Wiring length should be 1 inch if operating frequency reaches or exceeds 75MHz. Ipari wiwọn ti o pọju fun awọn eerun GaAs yẹ ki o jẹ 0.3 inches. Ti eyi ba ti kọja, iṣoro laini gbigbe kan wa.

3. Daradara gbero topology ti cabling

Another way to solve the transmission line effect is to choose the correct routing path and terminal topology. Topology cabling n tọka si ọkọọkan cabling ati eto ti okun nẹtiwọọki kan. Nigbati a ba lo awọn ẹrọ imọ-ẹrọ iyara to ga, ami ifihan pẹlu awọn ẹgbẹ iyipada yiyara yoo jẹ idibajẹ nipasẹ awọn ẹka ti ẹhin mọto ayafi ti ipari ẹka naa ba kuru pupọ. Ni gbogbogbo, afisona PCB gba awọn topologies ipilẹ meji, eyun afisona Daisy Chain ati pinpin Star.

Fun okun waya daisy-chain, wiwẹrẹ bẹrẹ ni opin awakọ ati de opin gbigba kọọkan ni ọwọ. If a series resistor is used to change the signal characteristics, the position of the series resistor should be close to the driving end. Iṣakojọpọ pq Daisy jẹ ti o dara julọ ni ṣiṣakoso kikọlu ibaramu giga ti cabling. Sibẹsibẹ, iru wiwu yii ni oṣuwọn gbigbe ti o kere julọ ati pe ko rọrun lati kọja 100%. Ninu apẹrẹ gangan, a fẹ lati ṣe ipari ẹka ni wiwọn pq Daisy ni kukuru bi o ti ṣee, ati iye ipari gigun ailewu yẹ ki o jẹ: Idaduro Stub < = Trt * 0.1.

Fun apẹẹrẹ, ẹka pari ni awọn iyika TTL iyara to ga julọ yẹ ki o kere ju awọn inṣisi 1.5 gigun. Topology yii gba aaye wiwọn kere si ati pe o le fopin si nipasẹ ibaramu alatako kan. Bibẹẹkọ, ọna wiwọn yii jẹ ki gbigba ifihan ni olugba ifihan ti o yatọ kii ṣe amuṣiṣẹpọ.

The star topology can effectively avoid the problem of clock signal synchronization, but it is very difficult to finish the wiring manually on the PCB with high density. Lilo okun alaifọwọyi jẹ ọna ti o dara julọ lati pari wiwakọ irawọ. A terminal resistor is required on each branch. The value of the terminal resistance should match the characteristic impedance of the wire. Eyi le ṣee ṣe pẹlu ọwọ tabi nipasẹ awọn irinṣẹ CAD lati ṣe iṣiro awọn iye ikọja abuda abuda ati awọn iye resistance ibaamu ebute.

While simple terminal resistors are used in the two examples above, a more complex matching terminal is optional in practice. Aṣayan akọkọ jẹ ebute ibaamu RC. Awọn ebute ibaamu RC le dinku agbara agbara, ṣugbọn o le ṣee lo nikan nigbati iṣẹ ifihan jẹ idurosinsin. Ọna yii dara julọ fun sisẹ ifihan ifihan laini aago. Alailanfani ni pe kapasito ninu ebute ibaamu RC le ni ipa apẹrẹ ati iyara itankale ti ifihan.

The series resistor matching terminal incurs no additional power consumption, but slows down signal transmission. This approach is used in bus-driven circuits where time delays are not significant. Ibudo ibaamu jara jara tun ni anfani ti idinku nọmba awọn ẹrọ ti a lo lori igbimọ ati iwuwo awọn isopọ.

The final method is to separate the matching terminal, in which the matching element needs to be placed near the receiving end. Anfani rẹ ni pe kii yoo fa ifihan agbara si isalẹ, ati pe o le dara pupọ lati yago fun ariwo. Ti a lo ni igbagbogbo fun awọn ami titẹ sii TTL (ACT, HCT, FAST).

In addition, the package type and installation type of the terminal matching resistor must be considered. SMD surface mount resistors generally have lower inductance than through-hole components, so SMD package components are preferred. There are also two installation modes for ordinary straight plug resistors: vertical and horizontal.

Ni ipo iṣagbesori inaro, resistance naa ni PIN fifẹ kukuru, eyiti o dinku itutu igbona laarin resistance ati igbimọ Circuit ati jẹ ki ooru resistance ni irọrun ni irọrun si afẹfẹ. Ṣugbọn fifi sori ẹrọ inaro to gun yoo pọ si inductance ti resistor. Horizontal installation has lower inductance due to lower installation. However, the overheated resistance will drift, and in the worst case, the resistance will become open, resulting in PCB wiring termination matching failure, becoming a potential failure factor.

4. Awọn imọ -ẹrọ miiran ti o wulo

Ni ibere lati dinku iṣipopada foliteji tionkojalo lori ipese agbara IC, o yẹ ki o fi kapasito ti o pọ sii kun si chiprún IC. Eyi ni imukuro imukuro ipa ti awọn burrs lori ipese agbara ati dinku itankalẹ lati lupu agbara lori igbimọ ti a tẹjade.

Ipa didan burr jẹ ti o dara julọ nigbati kapasito decoupling ti sopọ taara si ẹsẹ ipese agbara ti Circuit iṣọpọ dipo si Layer ipese agbara. Eyi ni idi ti diẹ ninu awọn ẹrọ ni awọn kapasito fifọ ni awọn iho wọn, lakoko ti awọn miiran nilo aaye laarin kapasito fifọ ati ẹrọ lati jẹ kekere to.

Eyikeyi iyara giga ati awọn ẹrọ agbara agbara giga yẹ ki o gbe papọ bi o ti ṣee ṣe lati dinku iṣipopada tionkoja ti folti ipese agbara.

Laisi fẹlẹfẹlẹ agbara, awọn laini agbara gigun ṣe lupu laarin ifihan ati lupu, ti n ṣiṣẹ bi orisun ti itankalẹ ati Circuit inductive.

Cabling ti n ṣe lupu ti ko kọja nipasẹ okun nẹtiwọọki kanna tabi okun miiran ni a pe ni lupu ṣiṣi. If the loop passes through the same network cable, other routes form a closed loop. Ni awọn ọran mejeeji, ipa eriali (eriali laini ati eriali oruka) le waye.