One Basic concept of perforation

Through hole (VIA) is an important part of Multilayer PCB, and the cost of drilling holes usually accounts for 30% to 40% of the cost of PCB board making. Simply put, every hole on a PCB can be called a pass hole. In terms of function, the hole can be divided into two categories: one is used for the electrical connection between layers; The other is used for device fixation or positioning. In terms of the process, these through-holes are generally divided into three categories, namely blind via, buried via and through via. Blind holes are located on the top and bottom surfaces of the PRINTED circuit board and have a certain depth for connecting the surface circuit to the inner circuit below. The depth of the holes usually does not exceed a certain ratio (aperture). Buried holes are connection holes in the inner layer of the printed circuit board that do not extend to the surface of the printed circuit board. The two types of holes are located in the inner layer of the circuit board, which is completed by the through-hole molding process before lamination, and several inner layers may be overlapped during the formation of the through-hole. The third type, called through-holes, runs through the entire circuit board and can be used for internal interconnections or as mounting and locating holes for components. Because the through hole is easier to implement in the process, the cost is lower, so most printed circuit boards are used it, rather than the other two kinds of through hole. The following through holes, without special explanation, shall be considered as through holes.

PCB through hole basic concept and through hole method introduction

From a design point of view, a through-hole is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole. The size of these two parts determines the size of the through-hole. Obviously, in the design of high-speed, high-density PCB, the designer always wants the hole as small as possible, this sample can leave more wiring space, in addition, the smaller the hole, its own parasitic capacitance is smaller, more suitable for high-speed circuit. But the hole size reduction at the same time brings the cost increase, and the size of the hole can not be reduced without limit, it is limited by drilling (drill) and plating (plating) and other technology: the smaller the hole, the longer the time it takes to drill, the easier it is to deviate from the center position; When the depth of the hole is more than 6 times the diameter of the hole, it is impossible to guarantee the uniform copper plating of the hole wall. For example, if the thickness (through-hole depth) of a normal 6-layer PCB board is 50Mil, then the minimum hole diameter that PCB manufacturers can provide is 8Mil. With the development of laser drilling technology, the size of drilling can also be smaller and smaller. Generally, the diameter of the hole is less than or equal to 6Mils, we call it micro hole. Microholes are often used in HDI (high density Interconnect structure) design. Microhole technology allows the hole to be hit directly on the pad (VIA-in-pad), which greatly improves circuit performance and saves wiring space.

The through-hole on the transmission line is a break point of impedance discontinuity, which will cause the reflection of the signal. Generally, the equivalent impedance of the through-hole is about 12% lower than that of the transmission line. For example, the impedance of the 50ohm transmission line will decrease by 6 ohm when it passes through the through-hole (the specific is also related to the size of the through-hole and the plate thickness, but not an absolute decrease). However, the reflection caused by the discontinuity of impedance through the hole is actually very small, and its reflection coefficient is only :(44-50)/(44+50) =0.06. The problems caused by the hole are more focused on the influence of parasitic capacitance and inductance.

Parasitic capacitance and inductance through the hole

The parasitic stray capacitance exists in the hole itself. If the diameter of the welding resistance zone of the hole on the laying layer is D2, the diameter of the welding pad is D1, the thickness of the PCB board is T, and the dielectric constant of the substrate is ε, the parasitic capacitance of the hole is approximately C=1.41εTD1/ (D2-D1).

The main effect of parasitic capacitance on the circuit is to prolong the signal rise time and reduce the circuit speed. For example, for a PCB board with a thickness of 50Mil, if the diameter of the through-hole pad is 20Mil (the diameter of the borehole is 10Mils) and the diameter of the solder block is 40Mil, we can approximate the parasitic capacitance of the through-hole by the formula above: C=1.41×4.4×0.050×0.020/ (0.040-0.020) =0.31pF the rise time change caused by capacitance is roughly as follows: T10-90= 2.2c (Z0/2) =2.2×0.31x (50/2) =17.05ps From these values, it can be seen that although the effect of rising delay and slowing caused by parasitic capacitance of a single through-hole is not very obvious, if the through-hole is used for switching between layers for multiple times, multiple through-holes will be used. Be careful in your design. In practical design, parasitic capacitance can be reduced by increasing the distance between the hole and the copper laying zone (anti-pad) or by reducing the diameter of the pad. In the design of high-speed digital circuit, the parasitic inductance of the through-hole is more harmful than that of the parasitic capacitance. Its parasitic series inductance will weaken the contribution of bypass capacitance and reduce the filtering effectiveness of the entire power system. We can simply calculate the parasitic inductance of a through-hole approximation using the following empirical formula: L=5.08h [ln (4h/d) +1]

Where L refers to the inductance of the hole, H is the length of the hole, and D is the diameter of the central hole. It can be seen from the equation that the diameter of the hole has little influence on the inductance, while the length of the hole has the greatest influence on the inductance. Still using the above example, the inductance out of the hole can be calculated as:

L=5.08×0.050 [ln (4×0.050/0.010) +1] = 1.015nh If the signal rise time is 1ns, then the equivalent impedance size is: XL=πL/T10-90=3.19 ω. This impedance cannot be ignored in the presence of high frequency current. In particular, the bypass capacitor has to pass through two holes to connect the supply layer to the formation, thus doubling the parasitic inductance of the hole.

Three, how to use the hole

Through the above analysis of the parasitic characteristics of the through-holes, we can see that in high-speed PCB design, the seemingly simple through-holes often bring great negative effects to the circuit design. In order to reduce the adverse effects of the parasitic effect of the hole, we can try to do as follows in the design:

1. Considering the cost and signal quality, a reasonable hole size is selected. If necessary, consider using different sizes of holes. For example, for power or ground cables, consider using larger sizes to reduce impedance, and for signal wiring, use smaller holes. Of course, as the hole size decreases, the corresponding cost will increase.

2. The two formulas discussed above show that the use of thinner PCB boards helps to reduce the two parasitic parameters of the perforations.

3. The signal wiring on the PCB board should not change layers as far as possible, that is to say, do not use unnecessary holes as far as possible.

4. The pins of the power supply and the ground should be drilled in the nearest hole, and the lead between the hole and the pins should be as short as possible. Multiple through-holes can be considered in parallel to reduce equivalent inductance.

5. Some ground holes are placed near the holes of signal layering in order to provide the nearest loop for the signal. You can even put a lot of extra ground holes on the PCB. Of course, you need to be flexible in your design. The through-hole model discussed above is a situation where there are pads in each layer. Sometimes, we can reduce or even remove pads in some layers. Especially in the case of the hole density is very large, it may lead to the formation of a cut off circuit groove in the copper layer, to solve such a problem in addition to moving the location of the hole, we can also consider the hole in the copper layer to reduce the size of the pad.

6. For high – speed PCB boards with higher density, micro – holes can be considered.