V mnohých prípadoch, PCB wiring will pass through holes, test spot pads, short stub lines, etc., all of which have parasitic capacitance, which will inevitably affect the signal. The influence of the capacitance on the signal should be analyzed from the transmitting end and the receiving end, and it has an effect on the starting point and the end point.

First click to see the impact on the signal transmitter. When a rapidly rising step signal reaches the capacitor, the capacitor is charged quickly. The charging current is related to how fast the signal voltage rises. The charging current formula is: I=C*dV/dt. The higher the capacitance, the higher the charging current, the faster the signal rise time, the smaller dt, also make the higher the charging current.

We know that the reflection of a signal is related to the change in impedance that the signal senses, so for analysis, let’s look at the change in impedance that the capacitance causes. At the initial stage of capacitor charging, impedance is expressed as:

Here, dV is actually the voltage change of step signal, dt is the signal rise time, and the capacitance impedance formula becomes:

From this formula, we can get a very important information, when the step signal is applied to the initial stage at both ends of the capacitor, the capacitor’s impedance is related to the signal rise time and its capacitance.

Usually at the initial stage of capacitor charging, the impedance is very small, less than the characteristic impedance of wiring. The negative reflection of the signal occurs at the capacitor, and the negative voltage signal is superimposed with the original signal, resulting in the downthrust of the signal at the transmitter and the non-monotonic of the signal at the transmitter.

For the receiving end, after the signal reaches the receiving end, positive reflection occurs, the reflected signal reaches the capacitor position, that kind of negative reflection occurs, and the negative reflection voltage reflected back to the receiving end also causes the signal at the receiving end to generate downrush.

In order for the reflected noise to be less than 5% of the voltage swing, which is tolerable for the signal, the impedance change must be less than 10%. So what should the capacitance impedance be? Capacitance impedance is a parallel impedance, and we can use the parallel impedance formula and reflection coefficient formula to determine its range. For this parallel impedance, we want the capacitance impedance to be as large as possible. Assuming that the capacitance impedance is K times of the PCB wiring characteristic impedance, the impedance felt by the signal at the capacitor can be obtained according to the parallel impedance formula:

That is, according to this ideal calculation, the impedance of the capacitor must be at least 9 times the characteristic impedance of the PCB. In fact, as the capacitor is charged, the impedance of the capacitor increases and does not always remain the lowest impedance. In addition, each device can have parasitic inductance, which increases the impedance. So this nine-fold limit can be relaxed. In the following discussion, assume that the limit is 5 times.

With an indicator of impedance, we can determine how much capacitance can be tolerated. The 50 ohms characteristic impedance on the circuit board is very common, so I used 50 ohms to calculate it.

It is concluded that:

In this case, if the signal rise time is 1ns, the capacitance is less than 4 picograms. Conversely, if the capacitance is 4 picograms, the signal rise time is 1ns at best. If the signal rise time is 0.5ns, this 4 picograms capacitance will cause problems.

The calculation here is only to explain the influence of capacitance, the actual circuit is very complex, more factors need to be considered, so whether the calculation here is accurate is not practical significance. The key is to understand how capacitance affects the signal through this calculation. Once we have a perceptual understanding of the impact of each factor on the circuit board, we can provide necessary guidance for the design and know how to analyze problems when they occur. Accurate estimates require software emulation.

záver:

1. The capacitive load during PCB routing causes the signal of transmitter end to produce downrush, and the signal of receiver end will also produce downrush.

2. The tolerance of capacitance is related to the signal rise time, the faster the signal rise time, the smaller the tolerance of capacitance.