1. How to choose PCB板?

PCB board selection must meet the design requirements and mass production and cost of the balance between. The design requirements include electrical and mechanical parts. This is usually important when designing very fast PCB boards (frequencies greater than GHz). For example, the fr-4 material commonly used today may not be suitable because the dielectric loss at several GHz has a great effect on signal attenuation. In the case of electricity, pay attention to the dielectric constant and dielectric loss at the designed frequency.

2、如何避免高频干扰？

The basic idea of avoiding high frequency interference is to minimize the interference of high frequency signal electromagnetic field, also known as Crosstalk. 您可以增加高速信号和模拟信号之间的距离，或者为模拟信号添加接地保护/分流走线。 Also pay attention to the digital ground to analog ground noise interference.

3. How to solve the problem of signal integrity in high-speed design?

信号完整性基本上是阻抗匹配的问题。 The factors that affect impedance matching include signal source architecture, output impedance, cable characteristic impedance, load side characteristic, and cable topology architecture. 解决办法是 * 终止并调整电缆的拓扑结构。

4. How to realize differential wiring?

The wiring of the difference pair has two points to pay attention to. One is that the length of the two lines should be as long as possible, and the other is that the distance between the two lines (determined by the difference impedance) should always remain constant, that is, to keep parallel. There are two parallel modes: one is that the two lines run on the same side-by-side layer, and the other is that the two lines run on two adjacent layers of the upper and lower layers. 通常，前者的并排实现更为常见。

5、只有一个输出端的时钟信号线如何实现差分接线？

要使用差分接线必须是信号源和接收端也是差分信号才有意义。 So it is impossible to use differential wiring for a clock signal with only one output.

6、接收端的差分线对之间可以加匹配电阻吗？

通常在接收端的一对差分线之间加上匹配电阻，其值应等于差分阻抗的值。 信号质量会更好。

7、为什么差分对的走线要最近且平行？

The wiring of difference pairs should be appropriately close and parallel. The proper height is due to the difference impedance, which is an important parameter in designing difference pairs. 还需要并行以保持差分阻抗的一致性。 如果两条线或远或近，差分阻抗就会不一致，从而影响信号完整性和TIming延迟。

8、在实际布线中如何处理一些理论冲突？

(1). Basically, it is right to separate modules/numbers. Care should be taken not to cross the MOAT and not to let the power supply and signal return current path grow too large.

(2). Crystal oscillator is a simulated positive feedback oscillating circuit, and stable oscillating signals must meet the specifications of loop gain and phase, which are prone to interference, even with ground guard traces may not be able to completely isolate interference. And too far away, the noise on the ground plane will also affect the positive feedback oscillation circuit. Therefore, be sure to make the crystal oscillator and chip as close as possible.

(3). Indeed, there are many conflicts between high-speed wiring and EMI requirements. 但其基本原理是由于EMI加入的电阻电容或铁氧体磁珠，不能导致信号的某些电气特性不符合规范。 Therefore, it is best to use the technique of arranging wiring and PCB stacking to solve or reduce EMI problems, such as high-speed signal lining. Finally, resistor capacitance or Ferrite Bead method was used to reduce the damage to the signal.

9、如何解决高速信号手动接线和自动接线的矛盾？

Nowadays, most of the automatic cabling devices in strong cabling software have set constraints to control the winding mode and the number of holes. EDA companies sometimes vary widely in setting the capabilities and constraints of winding engines. For example, whether there are enough constraints to control how serpenTIne lines wind, whether there are enough constraints to control the spacing of difference pairs, etc. This will affect whether the automatic wiring out of the wiring can conform to the designer’s idea. In addition, the difficulty of manual wiring adjustment is also absolutely related to the ability of the winding engine. 例如，线材的推料能力，通孔的推料能力，甚至铜镀层上的线材的推料能力等等。 所以，选择一台绕线机能力强的电缆车，才是解决之道。

10. About Test Coupon.

The Test Coupon is used to measure whether the characteristic impedance of the PRODUCED PCB board meets the design requirements by using the Time Domain Reflectometer (TDR). 一般情况下，要控制的阻抗有单​​线和差分对两种情况。 因此，测试卡上的线宽和线间距（如果有差异）应与被控制的线相同。 The most important thing is the location of the grounding point. 为了降低地线的电感值，TDR 探头的接地点通常非常靠近探头尖端。 因此，在测试卡上测量信号点和接地点的距离和方法应与所使用的探头相适应。

11. In high-speed PCB design, the blank area of the signal layer can be copper-coated, and how to distribute copper-coated on the grounding and power supply of multiple signal layers?

Generally in the blank area copper coating most of the case is grounded. 在高速信号线旁边敷铜时，只需注意敷铜与信号线的距离，因为敷铜会降低线路的特性阻抗。 Also be careful not to affect the characteristic impedance of other layers, as in the dual stripline construction.

12、电源平面上方的信号线能否用微带线模型计算特征阻抗？ 可以使用带状线模型计算电源和地平面之间的信号吗？

Yes, both the power plane and the ground plane must be considered as reference planes when calculating the characteristic impedance. 例如四层板：顶层-电源层-地层-底层。 在这种情况下，顶层布线特性阻抗模型是一个以电源平面为参考平面的微带线模型。

13. Can test points automatically generated by software on high density PCB meet the test requirements of mass production in general?

通用软件自动生成的测试点能否满足测试需求，取决于增加的测试点的规格是否满足试验机的要求。 另外，如果布线过于密集，添加测试点的规范比较严格，可能无法在线路的每一段自动添加测试点，当然需要手动完成测试点。

14、增加测试点是否会影响高速信号的质量？

是否影响信号质量取决于测试点的添加方式和信号的速度。 Basically, additional test points (not via or DIP pin as test points) can be added to the line or pulled out of the line. The former is equivalent to adding a very small capacitor on the line, the latter is an extra branch. Both of these two conditions have more or less influence on high-speed signals, and the degree of influence is related to the frequency speed and edge rate of signal. The influence can be obtained through simulation. 原则上测试点越小越好（当然要满足测试机的要求）分支越短越好。

15. 多个PCB系统，板间如何接地？

When the signal or power supply between each PCB board is connected to each other, for example, A board has power supply or signal to B board, there must be an equal amount of current from the floor flow back to A board (this is Kirchoff current law). The current in this layer will find its way back to the lowest impedance. Therefore, the number of pins assigned to the formation should not be too low at each interface, either power or signal connection, to reduce impedance and thus reduce formation noise. It is also possible to analyze the entire current loop, especially the larger part of the current, and adjust the connection of the ground or ground to control the flow of the current (for example, to create a low impedance in one place so that most of the current flows through that place), reducing the impact on other more sensitive signals.