PCB usoro wiring na -aga n’ihu na -akawanye mma, na usoro ịgbanye ọkụ nwere ike belata ogologo waya ma hapụ ohere PCB ọzọ. Ngwa wiwi PCB a na -ejedebe site na nhazi waya kwụ ọtọ yana enweghị wired nwere aka ike. Iwepu ihe mgbochi ndị a nwere ike imeziwanye ogo wiwi.

Let’s start with some terminology. Anyị na -akọwa wiwi Angle aka ike dị ka eriri waya site na iji akụkụ na radian aka ike. Ọ bụ ụdị wiwi waya, mana ejedebeghị na iji naanị ogo 90 na akụkụ ahịrị n’ahịrị 45. Topological wiring is wire wiring that does not adhere to grids and coordinates and does not use regular or irregular grids like shape-based wiring. Ka anyị kọwaa okwu mgbanwe wiring dị ka wiring waya na-enweghị ụdị edozi nke na-enyere mgbako mgbazinye oge iji nweta ohere mgbanwe ndị a. Naanị arcs sitere na ihe mgbochi na tangents ha na -ahụkarị ka a na -eji wee mepụta ahịrị ahịrị. (Obstacles include pins, copper foil, forbidden areas, holes and other objects) part of the circuit of two PCB models. Waya akwụkwọ ndụ akwụkwọ ndụ na -acha ọbara ọbara na -agba na ọkwa dị iche iche nke ihe nlereanya PCB. The blue circles are the perforations. The red element is highlighted. There are also some red round pins. Use only line segments and models with an Angle of 90 degrees between them. Ọgụgụ 1B bụ PCB nlereanya na -eji arcs na akụkụ aka ike. Wiring at any Angle may seem strange, but it does have many advantages. The way it is wired is very similar to how engineers wired it by hand half a century ago. Na -egosi ezigbo PCB mepụtara na 1972 nke ụlọ ọrụ America a na -akpọ Digibarn maka wiring aka zuru oke. This is a PCB board based on Intel8008 computer. Wiring Angle wiring gosiri na Ọgụgụ 2 yiri nke ahụ. Kedu ihe kpatara ha ga -eji jiri eriri ọkụ Angle aka ike? N’ihi na ụdị wiring a nwere ọtụtụ uru. Arbitrary Angle wiring has many advantages. Nke mbụ, ịghara iji akụkụ dị n’etiti ngalaba ahịrị na -azọpụta PCB ohere (polygons na -ewekarị ohere karịa tangents). Traditional automatic cablers can place only three wires between adjacent components (see left and center in Figure 3). Agbanyeghị, mgbe ị na -ebugharị n’akụkụ ọ bụla, enwere ohere zuru ezu iji tinye wires 4 n’otu ụzọ ahụ na -enweghị imebi nyocha nyocha (DRC). Ka e were ya na anyị nwere mgbawa ọnọdụ dị mma ma chọọ ijikọ atụdo mgbawa na mkpọ abụọ ọzọ. Using only 90 degrees takes up a lot of space. Iji eriri ikuku na -enweghị isi nwere ike ibelata ohere dị n’etiti mgbawa na atụdo ndị ọzọ, ebe ị na -ebelata akara ukwu. In this case, the area was reduced from 30 square centimeters to 23 square centimeters. Ịtụgharị mgbawa n’akụkụ ọ bụla nwekwara ike nye nsonaazụ kacha mma. In this case, the area was reduced from 23 square centimeters to 10 square centimeters. It shows a real PCB. Arbitrary Angle wiring with rotating chip function is the only wiring method for this circuit board. Nke a abụghị naanị tiori, kamakwa ọ bụ azịza bara uru (mgbe ụfọdụ ọ bụ naanị ihe ga -ekwe omume). Shows an example of a simple PCB. Topology cabler rụpụtara, ebe nsonaazụ akpaaka akpaka dabere n’ụdị kacha mma bụ foto PCB n’ezie. An automatic cabler based on optimal shape cannot do this because the components are rotated at arbitrary angles. Ị ga -achọkwu mpaghara, ma ọ bụrụ na ịgaghị atụgharị ihe mejupụtara ya, ekwesịrị ime ka ngwaọrụ ahụ buru ibu. Layout performance would be greatly improved without parallel segments, which are often a source of crosstalk. The level of crosstalk increases linearly as the length of parallel wires increases. As the spacing between parallel wires increases, crosstalk decreases quadratic. Let’s set the level of crosstalk produced by two parallel 1mm wires spaced d to e. Ọ bụrụ na enwere akụkụ dị n’etiti akụkụ waya, mgbe ahụ ka akụkụ a na -abawanye, ọkwa crosstalk ga -ebelata. The crosstalk does not depend on the length of the wire, but only on the Angle value: where α represents the Angle between the wire segments. Tụlee ụzọ atọ wiring ndị a. On the left side of Figure 8 (90 degree layout), there is the maximum wire length and the maximum emi value due to parallel line segments. In the middle of Figure 8 (45 degree layout), the wire length and emi values are reduced. On the right-hand side (at any Angle), the wire length is shortest and there are no parallel wire segments, so the interference value is negligible. So arbitrary Angle wiring helps to reduce the total wire length and significantly reduce electromagnetic interference. You also remember the effect on signal delay (conductors should not be parallel and should not be perpendicular to the PCB fiberglass). Advantages of flexible wiring Manual and automatic movement of components does not destroy the wiring in flexible wiring. Onye na -ahụ maka eriri na -agbakọ akpaaka kacha mma nke waya (na -eburu n’uche mkpa nchekwa dị mkpa). Cabling na -agbanwe agbanwe nwere ike belata oge achọrọ iji dezie topology, na -akwado ọtụtụ mgbake iji gboo mgbochi. Nke a na -egosi nhazi PCB nke na -agabiga oghere na isi ngalaba. N’oge mmegharị akpaka, a na-ahazi isi ngalaba waya na oghere ga-adị n’ọnọdụ kacha mma. In most computer-aided design (CAD) systems, the wiring interconnection problem is reduced to the problem of sequentially finding paths between pairs of points in a maze of pads, forbidden areas, and laid wires. Mgbe achọtara ụzọ, a na -edozi ya wee bụrụ akụkụ nke maze. Ọdịmma nke usoro wiring n’usoro bụ na nsonaazụ wiring nwere ike dabere n’usoro wiring. Mgbe ogo topological ka na -ezughị oke, nsogbu nke ‘ịrapara’ na -apụta na obere mpaghara mpaghara. But no matter which wire you rewire, it’s not going to improve the quality of the wiring. This is a serious problem in all CAD systems using sequential optimization. This is where the bending elimination process is useful. Ịgbagide waya na -ezo aka na ihe mere na waya n’ime otu netwọk ga -agagharị na ihe dị na netwọk ọzọ iji nweta ihe. Rewiring a wire will not correct this. Egosipụtara atụ ka ehulata. A lit red wire travels around a pin in the other network, and an unlit red wire connects to this pin. A na -egosipụta nsonaazụ nhazi akpaka. In the second case (on another layer), a lighted green wire is automatically rewired by changing the wiring layer (from green to red). Eliminate wire bending by automatically optimizing wire shape (approximate arcs with line segments just to show any Angle examples without arcs). (top) original design, (bottom) after eliminating bending design. A na -eme ka wired ndị na -acha uhie uhie pụta ìhè. N’ime osisi Steiner, a ga -ejikọ ahịrị niile dị ka akụkụ ruo oghere (ngwụcha na mgbakwunye). N’elu oghere ọhụrụ ọ bụla, akụkụ atọ ga -agbakọrịrị na ọ bụghị ihe karịrị akụkụ atọ ga -akwụsị. The Angle between the line segments that converge to the vertex shall not be less than 120 degrees. Ọ bụghị ihe siri ike iji Steiner rụọ ụdịrị ọnọdụ a zuru oke, mana ọ bụchaghị ntakịrị. Gray Steiner trees are not optimal, but black Steiner trees are. N’ime usoro nkwukọrịta bara uru, ekwesịrị ịtụle ụdị ihe mgbochi dị iche iche. Ha na -amachi ikike iji osisi almọnd na osisi Steiner rụọ osisi kacha nta na -agbatịkwu ogologo site na iji usoro jiometrị. The obstacles are shown in gray and we recommend starting at any end vertex. If there is more than one adjacent terminating vertex, you should choose one that allows you to continue using the second vertex. It depends on the Angle. Isi usoro ebe a bụ algorithm nke sitere na ike nke na-agbakọọ ike na-arụ ọrụ na oghere ọhụrụ ma na-akpali ha ugboro ugboro gaa na ebe nha anya (ịdị ukwuu na ntụzịaka nke ndị agha na-adabere na wires n’akụkụ isi alaka). Ọ bụrụ na akụkụ dị n’etiti otu ahịrị ahịrị jikọtara na vertex (njedebe ma ọ bụ mgbakwunye) erughị ogo 120, enwere ike ịgbakwunye isi ngalaba, wee nwee ike iji algọridim maka ịkwalite ọnọdụ vertex. It’s worth noting that simply sorting all angles in descending order and adding new vertices in that order doesn’t work, and the result is worse. After adding a new node, you should check the minimum of a subnet consisting of four pins:

1. If a vertex is added to the vicinity of another newly added vertex, check for the smallest four-pin network.

2. If the four-pin network is not minimal, select a pair of “diagonal” (belonging to the quadrilateral diagonal) endpoints or virtual terminal nodes (virtual terminal nodes – wire bends).

3. The line segment that connects the endpoint (virtual endpoint) to the nearest new vertex is replaced by the line segment that connects the endpoint (virtual endpoint) to the distant new vertex.

4. Use mechanical algorithms to optimize vertex positions.

This method does not guarantee to build the smallest network, but compared with other methods, it can achieve the smallest network length without grazing. Ọ na -enyekwa ohere maka ebe amachibidoro njikọ ebe ngwụcha, ọnụọgụ nke ọnụ ọnụ nwere ike bụrụ ihe aka ike.

Flexible wiring at any Angle has some other interesting advantages. For example, if you can automatically move many objects with the help of automatic real-time wire shape recalculation, you can create parallel serpentine lines. This cabling method makes better use of space, minimizes the number of iterations, and allows for flexible use of tolerances. If there are two serpentine lines interlaced with each other, the automatic cabler will reduce the length of one or both, depending on rule priority.

Consider the wiring of BGA components. In the traditional peripheral-to-center approach, the number of channels to the periphery is reduced by 8 with each successive layer (due to a reduction in perimeter). For example, a 28x28mm component with 784 pins requires 10 layers. Ụfọdụ akwa dị na eserese a agbanahụ wiring. Onyonyo 16 na -egosi otu ụzọ n’ụzọ anọ nke BGA. N’otu oge ahụ, mgbe ị na -eji usoro eriri “center to periphery”, ọnụọgụ ọwa achọrọ ịpụ na mpụta anaghị agbanwe site na oyi akwa ruo na oyi akwa. Nke a ga -ebelata oke ọnụọgụ. Maka nha akụrụngwa nke 28x28mm, akwa 7 zuru oke. Maka nnukwu akụrụngwa, ọ bụ mmeri. Figure 17 shows a quarter of the BGA. An example of BGA wiring is shown. When using the “center to periphery” cabling approach, we can complete the cabling of all networks. Arbitrary Angle topological cabler cable nwere ike ime nke a. Traditional automatic cablers cannot route this example. Shows an example of a real PCB where the engineer reduced the number of signal layers from 6 to 4 (compared to the specification). In addition, it took engineers only half a day to complete the wiring of the PCB.