Reduce the number of components and reduce the area of circuit board through wireless RF integration

In today’s wireless devices, more than half of the components on the circuit board are analog RF devices. Therefore, an effective way to reduce the circuit board area and power consumption is to carry out more large-scale RF integration and develop towards system level chip. This paper introduces the development status of RF integration, and puts forward some countermeasures and solutions to some of these problems.

A few years ago, the cellular phone market was dominated by single band and dual band single-mode phones, and the technology used was only??? Hold one or two cellular bands in all??? The same modulation method, multi-channel access scheme and protocol are adopted in the holding frequency band. In contrast, the design of today’s new generation of cellular phones is much more complex and can provide multi band and multi-mode??? It has Bluetooth personal area network, GPS positioning and other functions, and UWB and TV receiving functions have begun to appear. In addition, applications such as games, images, audio and video have become very common in mobile phones.

Wireless telephone is becoming a complex device called handheld personal entertainment center. Its development trend continues to bring more challenges to designers. Although compared with mobile phones with only voice function, the new generation of mobile phones have increased significantly in communication processing, application processing, the number of RF interfaces and integrated memory capacity, users still expect mobile phones to have smaller volume, streamlined shape, low price and large color display, It can provide standby and talk time similar to traditional voice phones. Maintaining the existing overall size and power consumption, but making the function increase exponentially, while maintaining the overall system cost unchanged, all these pose a lot of problems to the system designers.

Obviously, the problem involves all parts of the whole system design, as well as the suppliers of all wireless communication and entertainment content. One area that is particularly effective in reducing board area and power consumption is the RF part of wireless system design. This is because in today’s typical mobile phone, more than half of the components on the board are analog RF components, which together account for 30-40% of the whole board area, such as Bluetooth RF systems such as GPS and WLAN will also greatly increase the requirements for space.

The solution is to carry out more large-scale RF integration and finally develop into a fully integrated system level chip. Some designers put analog-to-digital converters into the antenna to reduce the total circuit board space required for RF functions. When semiconductor integration technology can integrate more functions in a single device, the number of discrete devices and the circuit board space used to accommodate these devices will be reduced accordingly. As the industry moves towards system level chip integration, designers will continue to find new technologies to meet the contradiction between higher RF complexity and longer battery life in small wireless devices.

Development status of RF integration

An important development of RF integration appeared about two years ago. At that time, the development of RF technology and digital baseband modem made it possible to replace superheterodyne RF devices with direct down conversion receivers in wireless mobile phones. Superheterodyne RF devices use multistage mixers, filters and multiple voltage controlled oscillators (VCOs), which have been well used for many years, but the integration of direct frequency conversion RF devices can greatly reduce the total number of GSM RF components. In the late 1990s, a typical single band superheterodyne RF subsystem included PA, antenna switch, LDO, small signal RF and vctcxo, requiring about 200 discrete devices; Today, we can design a direct frequency conversion system with four band function, which integrates VCO, VCXO and PLL loop filter, but its number of components is less than 50. Figure 1: four band GSM transceiver with high integration.

For example, the transceiver trf6151 (Figure 1) of Texas Instruments for GSM includes on-chip voltage regulator, VCO and VCO channel, PA power control, PLL loop filter edge blocker detection, LNA gain step-by-step control and VCXO.

For designers, advanced integration helps to overcome some major problems in wireless RF, among which the most basic one is the DC power supply and regulation of the transceiver. During a call, the battery voltage will change with the change of temperature and time. In addition, the noise coupling from TX VCO and Rx VCO power supply will also affect the performance of the whole system. Therefore, designers are faced with the problem of how to solve the RF circuit board regulator and most related passive components. Integrating these devices into the RF transceiver means that the only external component required is a simple decoupling capacitor, which is directly connected to the power supply, which not only simplifies the design, but also saves the circuit board space.

Another challenge for RF designers is VCO tuning range and locking time. In all analog VCO designs. Because it is often necessary to balance the locking time and tuning range, the loop filter is usually placed outside the chip. Sometimes, this can be solved in the software control of VCO tuning range. However, this method puts forward additional resource requirements for the overall development of telephone. When the digital tuning function is included in the VCO and can provide self calibration, an extended tuning range can be obtained, and the loop filter element can be placed in the chip. Obviously, this scheme can enable design engineers to simplify their work.

In order to obtain the transmitter power control required by the GSM system, PA manufacturers generally include this function in the power amplifier module (PAM). The power controller is usually composed of up to thousands of digital CMOS gates, which are made in an independent chip in PAM. This element will increase the cost of PAM by US $0.30 ~ 0.40. Integrating this function into RF devices will enable GaAs PAM manufacturers not to purchase digital CMOS circuits and install them into PAM. For an OEM producing thousands of products every month, removing this redundant component will greatly reduce their cost.

Another area where advanced integration can bring substantial savings is VCXO. In the past, expensive vctcxo modules were purchased and designed in RF devices as discrete components. Therefore, incorporating common components of vctcxo modules into RF devices can reduce costs and related design problems. Using trf6151, only a low-cost crystal and varactor are required to complete the function of vctcxo.

Despite these integration and design simplification, RF design engineers still face difficult choices, one of which is input sensitivity and Rx power consumption. It is well known that the larger the current used in the design of low noise amplifier (LNA), the lower the overall noise characteristics. The design engineer must determine the total power budget of the receiver and the sensitivity level requirements of the receiver. However, the noise does not decrease with the reduction of power. In fact, it is the opposite. Therefore, although it can meet the GSM standard specification, designers must often ask themselves whether it is worth paying the price in power consumption to achieve a certain sensitivity level. This question also explains why it is necessary for design engineers and IC manufacturers to cooperate closely in the whole design process. The feedback from design engineers can guide IC manufacturers to better serve the wireless industry when developing future RF products.

Developing towards SOC

Reducing the cost, power and complexity of wireless systems is very important to successfully meet the requirements of system integration. However, the development of high integration solutions for mobile phones requires the semiconductor industry to overcome complex technical obstacles. Some of these obstacles are rarely concerned by designers, because many of them do not want to know how SOC devices are made, As long as it can provide the required performance. Therefore, it is necessary to have a quick understanding of some process technologies, which will affect the capability and availability of devices used in cellular phone integration.

There are several feasible schemes for the integration of mobile phone RF electronic system. Firstly, a traditional RF architecture can be implemented in a relatively simple bipolar or BiCMOS process using traditional technology. The final RF chip can be assembled with mobile phone digital logic functions using multi chip packaging technology (system level packaging technology). Although this technology has many advantages, such as using familiar RF design methods and mature processes and technologies, it is difficult to commercialize due to the high cost and yield of test devices.

In addition, the integration of mobile phone electronic system can also be obtained by advanced BiCMOS (SiGe) wafer process. However, because the processing of SiGe HBT devices requires additional lithography process, the final chip will require an additional cost. At the same time, because SiGe BiCMOS technology can not use the most advanced lithography process, BiCMOS process usually lags behind the advanced digital CMOS process. These will bring great pressure to increase the characteristics of mobile phones and reduce costs. It can not be solved with a simple wafer process strategy, because this technology can not keep the system logic or digital part at the lowest possible price at all times. Therefore, monolithic integration of system baseband function RF part in BiCMOS (or SiGe) is not a good choice.

The final solution that can be considered is RF integration in CMOS, which also faces considerable challenges. Although there are several CMOS cellular RF designs, these designs are largely based on analog functions. It is difficult to implement analog mixers, filters and amplifiers with CMOS technology, and the power consumption is generally greater than SiGe BiCMOS scheme. With the development of process technology, CMOS rated level is getting lower and lower, which makes analog design more difficult. In the early stage of developing new processes, device modeling and process maturity generally can not meet the requirements of high-precision parameter modeling required for analog module design. However, the recently developed digital CMOS RF architecture makes monolithic CMOS integration more attractive.

These solutions also drive the semiconductor industry as manufacturers seek low-cost RF system level chip solutions. Although each integration scheme has difficulties, it is indeed surprising that RF component integration can reach such a high level. Overcoming these difficulties will take a big step forward in the design of wireless mobile phones and set the direction for greater integration in the near future.

Conclusion of this paper

There are still many difficulties in RF integration. Every RF device of modern mobile phone is faced with strict performance requirements. The sensitivity requirement is about – 106dbm (106db below 1 MW) or higher, and the corresponding level is only a few microvolts; In addition, selectivity, that is, the rejection ability of the useful channel to the adjacent frequency band (commonly referred to as blocking), should be in the order of 60dB; In addition, the system oscillator is required to operate under very low phase noise to prevent folding blocking energy from entering the receiving band. RF integration is very difficult because of the very high frequency and extremely demanding performance requirements.

Processing multi frequency standard brings a real challenge to the whole SOC frequency. It is hoped to reduce the excitation generated by in band signal transmission. The content of digital RF integration is much more than putting multiple RF components in one chip. A new architecture of hardware sharing is needed.

For system designers, the current simple, highly integrated and cost-effective semiconductor devices can greatly reduce the design complexity. At the same time, they can enrich the characteristics of wireless devices and keep the system size, battery life and cost unchanged. The new highly integrated RF devices can also eliminate some disputes in wireless design and save engineers’ valuable time.