With the increase of integrated circuit output switching speed and PCB bord density, Signal Integrity has become one of the issues that must be concerned in high-speed digital PCB design. The parameters of components and PCB board, the layout of components on PCB board, the wiring of high-speed Signal line and other factors, Can cause problems with signal integrity.

For PCB layouts, signal integrity requires a board layout that does not affect signal timing or voltage, while for circuit wiring, signal integrity requires termination elements, layout strategies, and wiring information. High signal speed on a PCB, incorrect placement of end components, or incorrect wiring of high-speed signals can cause signal integrity problems, which may cause the system to output incorrect data, the circuit to work improperly or not work at all. How to take signal integrity into full consideration and take effective control measures in PCB design has become a hot topic in PCB design industry.

Signal integrity Problem Good signal integrity means that the signal can respond with the correct timing and voltage level values when required. Os a choinne sin, nuair nach bhfreagraíonn an comhartha i gceart, tá fadhb sláine comhartha ann. Signal integrity problems can lead to or directly lead to signal distortion, timing errors, incorrect data, address and control lines, and system misoperation, or even system crash. In the process of PCB design practice, people have accumulated a lot of PCB design rules. In PCB design, the signal integrity of PCB can be better achieved by carefully referring to these design rules.

When designing PCB, we should first understand the design information of the whole circuit board, which mainly includes:

1. The number of devices, device size, device package, chip rate, whether PCB is divided into low speed, medium speed and high speed area, which is the interface input and output area;

2. The overall layout requirements, device layout location, whether there is a high power device, chip device heat dissipation special requirements;

3. Cineál líne comhartha, luas agus treo tarchuir, riachtanais rialaithe impedance na líne comhartha, treo luais bus agus staid tiomána, príomhchomharthaí agus bearta cosanta;

4. Cineál an tsoláthair chumhachta, an cineál talún, na ceanglais maidir le lamháltas torainn maidir le soláthar cumhachta agus talamh, socrú agus deighilt an tsoláthair chumhachta agus an eitleáin talún;

5. Cineálacha agus rátaí línte clog, foinse agus treo na línte clog, riachtanais mhoill clog, na riachtanais líne is faide.

Dearadh sraitheach PCB

After understanding the basic information of the circuit board, it is necessary to weigh the design requirements of the circuit board cost and signal integrity, and choose a reasonable number of wiring layers. At present, the circuit board has gradually developed from single layer, double layer and four layer to more multi-layer circuit board. Multi-layer PCB design can improve the reference surface of signal routing and provide backflow path for signal, which is the main measure to achieve good signal integrity. When designing PCB layering, follow the following rules:

1. The reference plane shall preferably be the ground plane. Both power supply and ground plane can be used as reference plane, and both have certain shielding function. Mar sin féin, tá éifeacht sciath an eitleáin soláthair cumhachta i bhfad níos ísle ná éifeacht an eitleáin talún mar gheall ar a impedance tréith níos airde agus an difríocht poitéinsil níos mó idir an plána soláthair cumhachta agus leibhéal na talún tagartha.

2. Digital circuit and analog circuit are layered. Where design costs permit, it is best to arrange digital and analog circuits on separate layers. If must want to arrange in same wiring layer, can use ditch, add earthing line, the method such as dividing line to remedy. Analog and digital power and ground must be separated, never mixed.

3. Ní thrasnaíonn príomhbhealach comhartha na sraitheanna cóngaracha an limistéar deighilte. Signals will form a large signal loop across the region and generate strong radiation. If the signal cable must cross the area when the ground cable is divided, a single point can be connected between the ground to form a connection bridge between the two ground points, and then the cable can be routed through the connection bridge.

4. Ba chóir go mbeadh eitleán talún réasúnta iomlán faoi dhromchla na comhpháirte. Ní mór sláine an eitleáin talún a choinneáil chomh fada agus is féidir don phláta ilteangach. De ghnáth ní cheadaítear do línte comhartha rith sa phlána talún.

5, high frequency, high speed, clock and other key signal lines should have adjacent ground plane. In this way, the distance between signal line and ground line is only the distance between PCB layers, so the actual current always flows in the ground line directly below the signal line, forming the smallest signal loop area and reducing radiation.

How to design the signal of integrity PCB

PCB layout design

Is í an eochair i ndearadh sláine comhartha an bhoird chlóite ná leagan amach agus sreangú, a bhfuil baint dhíreach aige le feidhmíocht PCB. Prior to layout, the PCB size must be determined to meet the function at the lowest possible cost. If the PCB is too large and distributed, the transmission line may be very long, resulting in increased impedance, reduced noise resistance, and increased cost. If the components are placed together, heat dissipation is poor, and coupling crosstalk may occur in adjacent wiring. Dá bhrí sin, caithfidh an leagan amach a bheith bunaithe ar aonaid fheidhmiúla an chiorcaid, agus comhoiriúnacht leictreamaighnéadach, diomailt teasa agus fachtóirí comhéadain á mbreithniú.

When laying out a PCB with mixed digital and analog signals, do not mix digital and analog signals. If analog and digital signals must be mixed, be sure to line vertically to reduce the effect of cross-coupling. The digital circuit, analog circuit, and noise-generating circuit on the circuit board should be separated, and the sensitive circuit should be routed first, and the coupling path between the circuits should be eliminated. Smaoinigh go háirithe ar an gclog, na línte athshocraithe agus cur isteach, ná comhthreomhar leis na línte seo leis na línte lasc ard srutha, ar shlí eile déanann comharthaí cúplála leictreamaighnéadacha damáiste dóibh, rud a fhágann go ndéantar athshocrú nó cur isteach gan choinne. The overall layout should follow the following principles:

1. Functional partition layout, analog circuit and digital circuit on PCB should have different spatial layout.

2. De réir an phróisis comhartha ciorcaid na haonaid chiorcaid fheidhmiúla a shocrú, ionas go sreabhann an comhartha chun an treo céanna a choinneáil.

3. Take the core components of each functional circuit unit as the center, and other components are arranged around it.

4. Shorten the connection between high-frequency components as much as possible and try to reduce their distribution parameters.

5. Easily disturbed components should not be too close to each other, input and output components should be far away.

How to design the signal of integrity PCB

Dearadh sreangú PCB

All signal lines should be classified before PCB wiring. First of all, clock line, sensitive signal line, and then high-speed signal line, in order to ensure that this kind of signal through the hole is enough, distribution parameters of good characteristics, and then general unimportant signal line.

Incompatible signal lines should be far away from each other and do not parallel wiring, such as digital and analog, high speed and low speed, high current and small current, high voltage and low voltage. Signal cables on different layers should be routed vertically to each other to reduce crosstalk. Is fearr socrú na línte comhartha a shocrú de réir treo sreafa an chomhartha. Níor cheart líne comhartha aschuir ciorcad a aistarraingt ar ais go limistéar na líne comhartha ionchuir. High-speed signal lines should be kept as short as possible to avoid interfering with other signal lines. Ar an bpainéal dúbailte, más gá, is féidir an sreang talún aonrúcháin a chur ar dhá thaobh na líne comhartha ardluais. Ba chóir sciath a chur ar gach líne clog ardluais ar an gclár iltaobhach de réir fhad na línte clog.

Is iad seo a leanas na prionsabail ghinearálta maidir le sreangú:

1. As far as possible to choose low density wiring design, and signal wiring as far as possible thickness consistent, conducive to impedance matching. For rf circuit, the unreasonable design of signal line direction, width and line spacing may cause cross interference between signal transmission lines.

2. As far as possible to avoid adjacent input and output wires and long-distance parallel wiring. Chun crosstalk na línte comhartha comhthreomhara a laghdú, is féidir an spásáil idir línte comhartha a mhéadú, nó is féidir criosanna aonrúcháin a chur isteach idir línte comhartha.

3. Beidh leithead na líne ar PCB aonfhoirmeach agus ní tharlóidh sóchán leithead líne. Níor cheart go n-úsáidfeadh lúb sreangú PCB cúinne 90 céim, ba chóir dó stua nó Uillinn 135 céim a úsáid, a mhéid is féidir chun leanúnachas an bhacainn líne a choinneáil.

4. Minimize the area of the current loop. The external radiation intensity of current-carrying circuit is proportional to the current passing through, the loop area and the square of signal frequency. Reducing the current loop area can reduce the ELECTROMAGNETIC interference of PCB.

5. As far as possible to reduce the length of the wire, increase the width of the wire, is conducive to reducing the impedance of the wire.

6. For switch control signals, the number of SIGNAL PCB wiring that changes the state at the same time should be reduced as far as possible.