Me ka hoʻonui ʻia o ka hoʻololi ʻana o ka hoʻololi kaʻapuni i hoʻohui ʻia a Papa PCB density, Signal Integrity has become one of the issues that must be concerned in high-speed digital PCB design. The parameters of components and PCB board, the layout of components on PCB board, the wiring of high-speed Signal line and other factors, Can cause problems with signal integrity.

For PCB layouts, signal integrity requires a board layout that does not affect signal timing or voltage, while for circuit wiring, signal integrity requires termination elements, layout strategies, and wiring information. ʻO ka wikiwiki hōʻailona kiʻekiʻe ma kahi PCB, ka hoʻokomo hewa ʻana o nā ʻāpana hopena, a i ʻole ka uwea hewa ʻole o nā hōʻailona holo wikiwiki hiki ke hoʻopilikia i ka pono o ka hōʻailona, ​​​​e hiki ai i ka ʻōnaehana ke hoʻopuka i ka ʻikepili hewa, hana pono ʻole ke kaapuni. Pehea e lawe ai i ka pono hōʻailona i loko o ka noʻonoʻo piha a lawe i nā ana mana kūpono i ka hoʻolālā PCB ua lilo i kumuhana wela i ka ʻoihana hoʻolālā PCB.

Signal integrity Problem Good signal integrity means that the signal can respond with the correct timing and voltage level values when required. ʻO ka mea ʻāpiki, ke pane ʻole ka hōʻailona pono, aia kekahi pilikia pono kīnā ʻole. Hiki i nā pilikia kū pono i ka hōʻailona ke alakaʻi i a i ʻole ke alakaʻi pololei i ka distortion hōʻailona, ​​nā hewa o ka manawa, nā ʻikepili kūpono ʻole, nā helu a me nā laina kaohi, a me ka nalowale ʻana o ka ʻōnaehana. I ke kaʻina hana o ka hana hoʻolālā PCB, ua hōʻiliʻili nā kānaka i nā lula hoʻolālā PCB. Ma ka hoʻolālā PCB, hiki ke hoʻokō maikaʻi ʻia ka hōʻailona hōʻailona o ka PCB ma ka nānā pono ʻana i kēia mau lula hoʻolālā.

When designing PCB, we should first understand the design information of the whole circuit board, which mainly includes:

1. The number of devices, device size, device package, chip rate, whether PCB is divided into low speed, medium speed and high speed area, which is the interface input and output area;

2. The overall layout requirements, device layout location, whether there is a high power device, chip device heat dissipation special requirements;

3. ʻAno laina hōʻailona, ​​ka wikiwiki a me ke kuhikuhi ʻana, nā koi hoʻomalu impedance o ka laina hōʻailona, ​​ke kuhikuhi holo kaʻa a me ke kūlana hoʻokele, nā hōʻailona kī a me nā ana pale;

4. Ke ‘ano o ka lako mana, ke ‘ano o ka lepo, ka leo no ka ho’omanawanui ‘ana i nā koi no ka lako mana a me ka lepo, ka ho’onohonoho ‘ana a me ka māhele ‘ana o ka mana a me ka mokulele honua;

5. Nā ʻano a me nā helu o nā laina uaki, kumu a me ke kuhikuhi o nā laina uaki, nā koi hoʻolōʻihi uaki, nā koi laina lōʻihi loa.

Hoʻolālā papa PCB

Ma hope o ka hoʻomaopopo ʻana i ka ʻike maʻamau o ka papa kaapuni, pono ke kaupaona i nā koi hoʻolālā o ka papa kaapuni a me ka pono o ka hōʻailona, ​​a koho i kahi helu kūpono o nā papa uila. At present, the circuit board has gradually developed from single layer, double layer and four layer to more multi-layer circuit board. Multi-layer PCB design can improve the reference surface of signal routing and provide backflow path for signal, which is the main measure to achieve good signal integrity. When designing PCB layering, follow the following rules:

1. ʻO ka papa kuhikuhi e ʻoi aku ka maikaʻi o ka papa honua. Hiki ke hoʻohana ʻia ka lako mana a me ka mokulele honua ma ke ʻano he mokulele kūmole, a he mau hana pale kā lāua. Eia naʻe, ʻoi aku ka haʻahaʻa o ka hopena pale o ka mokulele hoʻolako mana ma mua o ka mokulele honua ma muli o kona ʻano impedance kiʻekiʻe a ʻoi aku ka nui o ka ʻokoʻa ma waena o ka mokulele lako mana a me ka pae honua kuhikuhi.

2. Digital circuit and analog circuit are layered. Ma kahi e ʻae ai nā kumukūʻai hoʻolālā, ʻoi aku ka maikaʻi e hoʻonohonoho i nā kaho uila a me nā aniani ma nā ʻāpana ʻokoʻa. If must want to arrange in same wiring layer, can use ditch, add earthing line, the method such as dividing line to remedy. Pono e hoʻokaʻawale i ka mana analog a me ka uila a me ka honua, mai huikau.

3. ʻAʻole hiki i ka hoʻokele hōʻailona kī o nā papa pili ke hele i ka māhele ʻāpana. E hoʻokumu nā hōʻailona i kahi puʻupuʻu hōʻailona nui ma ka ʻāina a hoʻoulu i ka radiation ikaika. If the signal cable must cross the area when the ground cable is divided, a single point can be connected between the ground to form a connection bridge between the two ground points, and then the cable can be routed through the connection bridge.

4. Pono e loa’a kahi papa honua holo’oko’a ma lalo o ka ili o nā mea. Pono e mālama i ka pono o ka mokulele honua a hiki i ka papa multilayer. ʻAʻole ʻae ʻia nā laina hōʻailona e holo ma ka mokulele honua.

5, ke alapine kiʻekiʻe, ke kiʻekiʻe wikiwiki, uaki a me nā laina hōʻailona kī ʻē aʻe e pili pono i ka mokulele honua. In this way, the distance between signal line and ground line is only the distance between PCB layers, so the actual current always flows in the ground line directly below the signal line, forming the smallest signal loop area and reducing radiation.

How to design the signal of integrity PCB

PCB layout design

ʻO ke kī o ka hoʻolālā pono hōʻailona o ka papa paʻi ka hoʻonohonoho a me nā uea, e pili pono ana i ka hana o PCB. Prior to layout, the PCB size must be determined to meet the function at the lowest possible cost. Inā nui a hāʻawi ʻia ka PCB, lōʻihi loa paha ka laina hoʻoili, e hopena ana i ka impedance hoʻonui, hoʻemi i ke kūpaʻa leo, a hoʻonui i ka uku. Inā hoʻokomo ʻia nā mea, ʻilihuna ka dissipation wela, a hiki i ka hoʻopili ʻana i ka crosstalk i nā uea pili. No laila, pono e hoʻokumu ʻia ka hoʻonohonoho ʻana i nā ʻāpana hana o ke kaapuni, ʻoiai e noʻonoʻo ana i ka hoʻohālikelike electromagnetic, ka wela a me nā mea pili.

Ke waiho ʻana i kahi PCB me nā hōʻailona kikohoʻe a me analog, mai hoʻohui i nā hōʻailona kikohoʻe a me ka analog. Inā pono e hui pū ʻia nā hōʻailona analog a me nā kikohoʻe, e hoʻopaʻa pono i ka laina pololei e hōʻemi i ka hopena o ka hui ʻana. Pono e hoʻokaʻawale ʻia ke kaapuni kikohoʻe, kaʻapuni analog, a me ke kaapuni hoʻoheheʻe leo ma ka papa kaapuni, a pono e hoʻokaʻawale mua ʻia ke kaapuni koʻikoʻi, a e hoʻopau ʻia ke ala hoʻohui ma waena o nā kaapuni. I ke kikoʻī, e noʻonoʻo i ka uaki, hoʻonohonoho hou a hoʻopau i nā laina, mai hoʻohālikelike i kēia mau laina me nā laina kuapo kiʻekiʻe o kēia manawa, a i ʻole maʻalahi ʻino ʻia e nā hōʻailona hoʻopili electromagnetic, e hoʻoiho a hoʻohoka ʻole paha. The overall layout should follow the following principles:

1. ʻO ka hoʻolālā ʻāpana hana, ka kaapuni analog a me ke kaapuni kikohoʻe ma PCB pono e loaʻa i kahi hoʻolālā spatial ʻokoʻa.

2. Wahi a ke kaʻina hōʻailona kaapuni e hoʻonohonoho i nā kikowaena kaapuni hana, i mea e kahe ai ka hōʻailona e mālama i ke ala like.

3. Take the core components of each functional circuit unit as the center, and other components are arranged around it.

4. Shorten the connection between high-frequency components as much as possible and try to reduce their distribution parameters.

5. ʻAʻole pono e pili kokoke nā mea hoʻopili maʻalahi i kekahi i kekahi, mamao loa nā mea hoʻokomo a me nā mea hoʻopuka.

How to design the signal of integrity PCB

Hoʻolālā uea PCB

Pono e hoʻokaʻawale ʻia nā laina hōʻailona a pau ma mua o ka uwila PCB. First of all, clock line, sensitive signal line, and then high-speed signal line, in order to ensure that this kind of signal through the hole is enough, distribution parameters of good characteristics, and then general unimportant signal line.

Incompatible signal lines should be far away from each other and do not parallel wiring, such as digital and analog, high speed and low speed, high current and small current, high voltage and low voltage. Pono e hoʻokuʻu ʻia nā kaula hōʻailona ma nā papa like ʻole i kekahi i kekahi e hōʻemi i ka crosstalk. Hoʻonohonoho maikaʻi ʻia ka hoʻonohonoho ʻana o nā laina hōʻailona e like me ke kuhikuhi kahe o ka hōʻailona. ʻAʻole pono e hoʻihoʻi ʻia ka laina hōʻailona hoʻopuka o kahi kaapuni i ka wahi laina hōʻailona hoʻokomo. High-speed signal lines should be kept as short as possible to avoid interfering with other signal lines. Ma ka papa ʻelua, inā pono, hiki ke hoʻohui ʻia ka uea honua kaʻawale ma nā ʻaoʻao ʻelua o ka laina hōʻailona kiʻekiʻe. Pono e pale i nā laina uaki wikiwiki holoʻokoʻa ma ka papa multilayer e like me ka lōʻihi o nā laina uaki.

ʻO nā loina maʻamau no ka uwila:

1. E like me ka hiki ke koho haʻahaʻa haʻahaʻa haʻahaʻa uea hoʻolālā, a me ka hōʻailona uea like me ka mamao hiki mānoanoa kūlike, conducive i impedance pili. No ka pōʻaiapuni RF, ka hoʻolālā kūpono ʻole o ke kuhikuhi laina laina, ka laulā a me ka hoʻokaʻawale ʻana i ka laina i ke keakea ʻana ma waena o nā laina hoʻoili hōʻailona.

2. E pale aku i na uwea hookomo a me na uwea puka e pili ana a me na uwea like like loa. No ka hoʻemi ʻana i ke kamaʻilio ʻana o nā laina hōʻailona like, hiki ke hoʻonui ʻia ka mamao ma waena o nā laina hōʻailona, ​​a i ʻole hiki ke hoʻokomo ʻia nā kāʻei kaʻawale ma waena o nā laina hōʻailona.

3. E laulā ka laulā laina ma PCB a ʻaʻohe laina laulā e hoʻololi ʻia. ʻAʻole pono i ka PCB uila kūlou ke hoʻohana i nā kekelē 90, pono e hoʻohana i ka arc a i ʻole 135 kekelē Angle, a hiki i ka hiki ke mālama i ka hoʻomau ʻana o ka impedance laina.

4. Minimize the area of the current loop. The external radiation intensity of current-carrying circuit is proportional to the current passing through, the loop area and the square of signal frequency. Reducing the current loop area can reduce the ELECTROMAGNETIC interference of PCB.

5. E like me ka hiki ke emi i ka lōʻihi o ka uea, e hoonui i ka laula o ka uea, mea conducive i ka hoemi i ka impedance o ka uea.

6. No ka hoʻololi ʻana i nā hōʻailona mana, pono e hoʻemi ʻia ka helu o nā uwila SIGNAL PCB e hoʻololi i ka mokuʻāina i ka manawa like.