Fa’atasi ai ma le fa’atuputeleina o feso’ota’iga feso’ota’iga tu’ufa’atasi ma le saoasaoa Laupapa PCB density, Signal Integrity has become one of the issues that must be concerned in high-speed digital PCB design. The parameters of components and PCB board, the layout of components on PCB board, the wiring of high-speed Signal line and other factors, Can cause problems with signal integrity.

For PCB layouts, signal integrity requires a board layout that does not affect signal timing or voltage, while for circuit wiring, signal integrity requires termination elements, layout strategies, and wiring information. Ole saoasaoa ole maualuga ile PCB, le sao le faʻatulagaina ole vaega mulimuli, poʻo le le saʻo ole faʻailo o le saoasaoa tele o faʻailo e mafai ona mafua ai faʻafitauli ile faʻamaoni ole faʻamaoni, e ono afua ai ona leaga le faʻatinoina ole faʻamaumauga, ole matagaluega e galue sese pe le aoga. Le faʻafefea ona ave faʻamaoniga faʻamaoni i le iloiloga atoa ma le faʻaogaina lelei o le pulea i le PCB design ua avea ma autu vevela i le PCB design alamanuia.

Signal integrity Problem Good signal integrity means that the signal can respond with the correct timing and voltage level values when required. I se isi itu, a le tali lelei le faʻailo, e i ai le faʻafitauli faʻamaoni faʻamaoni. Faʻafitauli faʻamaoni faʻamaoni e mafai ona taitai atu ai pe tuʻusaʻo atu ai i le faʻailoga faʻaletonu, taimi sese, le saʻo faʻamatalaga, tuatusi ma laina faʻatonutonu, ma le faʻaaogaina sese o le tino, poʻo le paʻu foi o le tino. I le faagasologa o le faiga PCB mamanu, ua faaputuputu tagata le tele o tulafono mamanu PCB. I le PCB design, o le faʻailoga faʻamaoni o le PCB e mafai ona sili atu lona ausiaina e ala i le vaʻai totoʻa i nei tulafono faʻavae.

Pe a fuafuaina PCB, e tatau ona tatou muamua malamalama i le mamanu faʻamatalaga o le atoa matagaluega laupapa, lea e masani ona aofia ai:

1. The number of devices, device size, device package, chip rate, whether PCB is divided into low speed, medium speed and high speed area, which is the interface input and output area;

2. The overall layout requirements, device layout location, whether there is a high power device, chip device heat dissipation special requirements;

3. Ituaiga laina faʻailo, saoasaoa ma faʻatonuga faʻatonuga, faʻatonutonu manaʻoga manaʻoga o laina laina, pasi saoasaoa faʻatonuga ma avetaʻavale tulaga, faʻailoga autu ma puipuiga puipuiga;

4. Ituaiga o le eletise, ituaiga o eleele, leo o le leo e manaʻomia mo le eletise ma le eleele, faʻatulagaina ma le vaevaeina o le eletise ma le vaalele;

5. Ituaiga ma fua faatatau o laina uati, punavai ma le itu o laina o le uati, manaoga tuai o le uati, laina pito sili ona umi.

PCB fa’apipi’i mamanu

A maeʻa ona malamalama i faʻamatalaga autu o le laupapa matagaluega, e tatau ona fuaina le manaʻoga o le mamanu o le tau o le laupapa matagaluega ma faʻamaonia le amiosaʻo, ma filifili se numera talafeagai o laina laina. At present, the circuit board has gradually developed from single layer, double layer and four layer to more multi-layer circuit board. Multi-layer PCB design can improve the reference surface of signal routing and provide backflow path for signal, which is the main measure to achieve good signal integrity. When designing PCB layering, follow the following rules:

1. O le vaalele fa’asino e tatau ona avea ma vaalele o le eleele. E mafai ona fa’aogaina uma le paoa ma le va’alele eleele e fai ma va’alele fa’asino, ma o lo’o i ai uma i la’ua galuega fa’apitoa e puipuia ai. Ae ui i lea, o le talipupuni o le malosi o le vaalele e sili atu ona maualalo nai lo le vaalele i luga o le eleele ona o le maualuga o le faʻalavelave faʻapitoa ma le tele o le eseesega i le va o le eletise eletise ma le tulaga o le eleele.

2. Digital circuit and analog circuit are layered. Le mea e faʻatagaina ai le tau o le tisaini, e sili ona lelei le faʻatulagaina o faʻafuainumera ma faʻasolosolo i luga o vaega eseese. If must want to arrange in same wiring layer, can use ditch, add earthing line, the method such as dividing line to remedy. Analog ma faafuainumera mana ma le eleele e tatau ona tuueseeseina, aua le fefiloi.

3. O le fa’ailo fa’ailo autu o fa’alava fa’atasi e le sopoia le vaega fa’asoa. O faailo o le a fausia ai se matasele tele faailoilo i luga o le itulagi ma maua ai le vevela malosi. If the signal cable must cross the area when the ground cable is divided, a single point can be connected between the ground to form a connection bridge between the two ground points, and then the cable can be routed through the connection bridge.

4. E tatau ona i ai se vaʻalele atoatoa atoa eleele lalo o le vaega luga. O le faʻamaoni o le vaalele e tatau ona tausia i le mamao e mafai ai mo le multilayer plate. Leai ni faʻailo laina e masani ona faʻatagaina e tamoʻe i le vaʻalele eleele.

5, maualuga taimi, maualuga saosaoa, uati ma isi ki faʻailoga laina tatau ona i ai vaʻalele eleele felavasaʻi. In this way, the distance between signal line and ground line is only the distance between PCB layers, so the actual current always flows in the ground line directly below the signal line, forming the smallest signal loop area and reducing radiation.

How to design the signal of integrity PCB

PCB layout design

O le ki o le faʻailoga o le faʻamaoni o le lolomiina o le laupapa lolomiina o le faʻatulagaina ma le faʻaogaina o laina, lea e fesoʻotaʻi saʻo ma le faʻatinoina o le PCB. Prior to layout, the PCB size must be determined to meet the function at the lowest possible cost. Afai e tele naua le PCB ma tufatufaina, o le laina faʻasalalau atonu e umi tele, e mafua ai le faʻateleina o le faʻalavelave, faʻaitiitia le leo, ma le faʻateleina o tau. Afai e tuʻu faʻatasia vaega, e leaga le faʻamamaina o le vevela, ma e ono tupu le faʻapipiʻiina o crosstalk i uaea felataʻi. O le mea lea, o le faʻatulagaina tatau ona faʻavae i luga o le aoga iunite o le taʻamilosaga, a o iloiloina electromagnetic ogatasi, vevela dissipation ma interface mea.

Pe a tuʻuina atu se PCB faʻatasi ai ma faʻailoga numera ma faʻailoga analog, aua le faʻafefiloi faʻailoga numera ma faʻailoga analog. Afai e tatau ona fa’afefiloi fa’ailoga analog ma numera, ia mautinoa e laina tu’usa’o e fa’aitiitia ai le a’afiaga o feso’ota’iga. E tatau ona tuueseese le taamilosaga numera, taamilosaga analog, ma le pisapisao i luga o le laupapa matagaluega, ma o le taamilosaga maaleale e tatau ona taʻavale muamua, ma e tatau ona faʻaumatia le ala faʻapipiʻi i le va o taʻaloga. Aemaise lava, mafaufau i le uati, toe setiina ma faʻalavelave laina, aua le tutusa nei laina ma laina kilia maualuga o loʻo i ai nei, a le o lea e faigofie ona faʻaleagaina e faʻamaufaʻailoga electromagnetic, mafua ai le toe faʻafuaseʻi poʻo le faʻalavelave. The overall layout should follow the following principles:

1. Faagaioiga vaeluaina vaevaega, analog taamilosaga ma numera faafuainumera luga PCB tatau ona i ai eseese vaʻaiga vateatea.

2. E tusa ma le faʻasologa o faʻailoilo faʻagasologa e faʻatulaga ai vaega faʻagaioia o gaioiga, ina ia mafai ai ona tafe le faʻailoga e tausisi i le itu e tasi.

3. Take the core components of each functional circuit unit as the center, and other components are arranged around it.

4. Shorten the connection between high-frequency components as much as possible and try to reduce their distribution parameters.

5. E le tatau ona latalata tele le tasi i le isi i mea e faʻalavelave ai, o mea e faʻaulu mai ma galuega e tatau ona mamao ese.

How to design the signal of integrity PCB

PCB uaea mamanu

O laina faʻailo uma e tatau ona faʻavasegaina i luma ole PCB uaea. First of all, clock line, sensitive signal line, and then high-speed signal line, in order to ensure that this kind of signal through the hole is enough, distribution parameters of good characteristics, and then general unimportant signal line.

Incompatible signal lines should be far away from each other and do not parallel wiring, such as digital and analog, high speed and low speed, high current and small current, high voltage and low voltage. O uaea fa’ailo i luga o fa’alava eseese e tatau ona fa’asasa’o le tasi i le isi e fa’aitiitia ai le fe’avea’i. O le faʻatulagaina o laina faʻailo e sili atu ona faʻatulagaina e tusa ai ma le tafe o le faʻailoga. O le laina faʻailoilo laina o se matagaluega le tatau ona toe sailia i tua i le sao laina laina vaega. High-speed signal lines should be kept as short as possible to avoid interfering with other signal lines. I luga o le faʻalua vaega, pe a manaʻomia, o le faʻaesea eleele uaea mafai ona faʻaopopoina i itu uma o le televave laina saini. O laina uati saoasaoa uma i luga ole laupapa multilayer e tatau ona puipuia e tusa ma le umi o uati laina.

O le lautele mataupu faavae mo wiring o:

1. Le mea e gata ai le mafai e filifili maualalo density faʻapipiʻiina mamanu, ma faʻailoga faʻamau i le mea e mafai ai mafiafia tumau, faʻamalosia i faʻafetaui tutusa. Mo le RF matagaluega, o le le talafeagai fuafua o faʻailo laina laina, lautele ma laina vavalalata ono mafua ai fevesiaʻi va i le va o faʻailo laina laina.

2. E tusa ma le mea e mafai ai e aloese ai mai tuaoi o mea e faʻaulu ai ma uaea eletise ma uaea tutusa mamao. Ina ia faʻaititia laina laina laina tutusa, o le vavalalata i le va o laina faʻailoga e mafai ona faʻateleina, pe mafai ona faʻaofiina fusipaʻu vavaeʻese i le va o laina faʻailo.

3. O le laina lautele i luga o PCB o le a avea tutusa ma leai se laina lautele mutation o le a tupu. PCB uaea piʻo le tatau ona faʻaaogaina 90 tikeri tulimanu, tatau ona faʻaaogaina arc poʻo le 135 tikeri Angle, i le mamao e mafai ai e faʻatumauina le faʻaauau o laina laina.

4. Minimize the area of the current loop. The external radiation intensity of current-carrying circuit is proportional to the current passing through, the loop area and the square of signal frequency. Reducing the current loop area can reduce the ELECTROMAGNETIC interference of PCB.

5. I le mamao e mafai ai e faʻaitiitia le umi o le uaea, faʻateleina le lautele o le uaea, e faʻamalosia e faʻaitiitia ai le faʻalavelave o le uaea.

6. Mo fesuiaʻiga faʻatonutonu faailo, o le numera o SIGNAL PCB faʻapipiʻiina e suia le setete i le taimi e tasi tatau ona faʻaititia i le mamao e mafai ai.