With the increase of integrated circuit output switching speed and Bord tal-PCB density, Signal Integrity has become one of the issues that must be concerned in high-speed digital PCB design. The parameters of components and PCB board, the layout of components on PCB board, the wiring of high-speed Signal line and other factors, Can cause problems with signal integrity.

For PCB layouts, signal integrity requires a board layout that does not affect signal timing or voltage, while for circuit wiring, signal integrity requires termination elements, layout strategies, and wiring information. High signal speed on a PCB, incorrect placement of end components, or incorrect wiring of high-speed signals can cause signal integrity problems, which may cause the system to output incorrect data, the circuit to work improperly or not work at all. How to take signal integrity into full consideration and take effective control measures in PCB design has become a hot topic in PCB design industry.

Signal integrity Problem Good signal integrity means that the signal can respond with the correct timing and voltage level values when required. Bil-maqlub, meta s-sinjal ma jirrispondix sewwa, hemm problema ta ‘integrità tas-sinjal. Signal integrity problems can lead to or directly lead to signal distortion, timing errors, incorrect data, address and control lines, and system misoperation, or even system crash. In the process of PCB design practice, people have accumulated a lot of PCB design rules. In PCB design, the signal integrity of PCB can be better achieved by carefully referring to these design rules.

When designing PCB, we should first understand the design information of the whole circuit board, which mainly includes:

1. The number of devices, device size, device package, chip rate, whether PCB is divided into low speed, medium speed and high speed area, which is the interface input and output area;

2. The overall layout requirements, device layout location, whether there is a high power device, chip device heat dissipation special requirements;

3. Tip ta ‘linja tas-sinjal, veloċità u direzzjoni tat-trasmissjoni, rekwiżiti ta’ kontroll tal-impedenza tal-linja tas-sinjal, direzzjoni tal-veloċità tax-xarabank u sitwazzjoni tas-sewqan, sinjali ewlenin u miżuri ta ‘protezzjoni;

4. Tip ta ‘provvista tal-enerġija, tip ta’ art, rekwiżiti ta ‘tolleranza tal-ħoss għall-provvista tal-enerġija u l-art, issettjar u segmentazzjoni tal-provvista tal-enerġija u pjan tal-art;

5. Types and rates of clock lines, source and direction of clock lines, clock delay requirements, longest line requirements.

PCB layered design

After understanding the basic information of the circuit board, it is necessary to weigh the design requirements of the circuit board cost and signal integrity, and choose a reasonable number of wiring layers. At present, the circuit board has gradually developed from single layer, double layer and four layer to more multi-layer circuit board. Multi-layer PCB design can improve the reference surface of signal routing and provide backflow path for signal, which is the main measure to achieve good signal integrity. When designing PCB layering, follow the following rules:

1. The reference plane shall preferably be the ground plane. Both power supply and ground plane can be used as reference plane, and both have certain shielding function. However, the shielding effect of the power supply plane is much lower than that of the ground plane because of its higher characteristic impedance and larger potential difference between the power supply plane and the reference ground level.

2. Digital circuit and analog circuit are layered. Where design costs permit, it is best to arrange digital and analog circuits on separate layers. If must want to arrange in same wiring layer, can use ditch, add earthing line, the method such as dividing line to remedy. Analog and digital power and ground must be separated, never mixed.

3. The key signal routing of adjacent layers does not cross the segmentation area. Signals will form a large signal loop across the region and generate strong radiation. If the signal cable must cross the area when the ground cable is divided, a single point can be connected between the ground to form a connection bridge between the two ground points, and then the cable can be routed through the connection bridge.

4. There should be a relatively complete ground plane below the component surface. L-integrità tal-pjan terren għandha tinżamm kemm jista ‘jkun possibbli għall-pjanċa b’ħafna saffi. L-ebda linja ta ‘sinjal normalment ma titħalla taħdem fil-pjan ta’ l-art.

5, high frequency, high speed, clock and other key signal lines should have adjacent ground plane. In this way, the distance between signal line and ground line is only the distance between PCB layers, so the actual current always flows in the ground line directly below the signal line, forming the smallest signal loop area and reducing radiation.

How to design the signal of integrity PCB

PCB layout design

Iċ-ċavetta tad-disinn tal-integrità tas-sinjal tal-bord stampat hija t-tqassim u l-wajers, li huma direttament relatati mal-prestazzjoni tal-PCB. Prior to layout, the PCB size must be determined to meet the function at the lowest possible cost. If the PCB is too large and distributed, the transmission line may be very long, resulting in increased impedance, reduced noise resistance, and increased cost. If the components are placed together, heat dissipation is poor, and coupling crosstalk may occur in adjacent wiring. Għalhekk, it-tqassim għandu jkun ibbażat fuq l-unitajiet funzjonali taċ-ċirkwit, filwaqt li jiġu kkunsidrati l-kompatibilità elettromanjetika, id-dissipazzjoni tas-sħana u l-fatturi ta ‘l-interface.

When laying out a PCB with mixed digital and analog signals, do not mix digital and analog signals. If analog and digital signals must be mixed, be sure to line vertically to reduce the effect of cross-coupling. The digital circuit, analog circuit, and noise-generating circuit on the circuit board should be separated, and the sensitive circuit should be routed first, and the coupling path between the circuits should be eliminated. In particular, consider the clock, reset and interrupt lines, do not parallel these lines with the high current switch lines, otherwise easily damaged by electromagnetic coupling signals, causing unexpected reset or interrupt. The overall layout should follow the following principles:

1. Functional partition layout, analog circuit and digital circuit on PCB should have different spatial layout.

2. According to the circuit signal process to arrange the functional circuit units, so that the signal flow to maintain the same direction.

3. Take the core components of each functional circuit unit as the center, and other components are arranged around it.

4. Shorten the connection between high-frequency components as much as possible and try to reduce their distribution parameters.

5. Easily disturbed components should not be too close to each other, input and output components should be far away.

How to design the signal of integrity PCB

Disinn tal-wajers tal-PCB

All signal lines should be classified before PCB wiring. First of all, clock line, sensitive signal line, and then high-speed signal line, in order to ensure that this kind of signal through the hole is enough, distribution parameters of good characteristics, and then general unimportant signal line.

Incompatible signal lines should be far away from each other and do not parallel wiring, such as digital and analog, high speed and low speed, high current and small current, high voltage and low voltage. Signal cables on different layers should be routed vertically to each other to reduce crosstalk. L-arranġament tal-linji tas-sinjal huwa l-aħjar irranġat skond id-direzzjoni tal-fluss tas-sinjal. Il-linja tas-sinjal tal-ħruġ ta ‘ċirkwit m’għandhiex tiġi ritrattata lura lejn iż-żona tal-linja tas-sinjal tad-dħul. High-speed signal lines should be kept as short as possible to avoid interfering with other signal lines. On the double panel, if necessary, the isolation ground wire can be added on both sides of the high-speed signal line. All high-speed clock lines on the multilayer board should be shielded according to the length of clock lines.

Il-prinċipji ġenerali għall-wajers huma:

1. As far as possible to choose low density wiring design, and signal wiring as far as possible thickness consistent, conducive to impedance matching. For rf circuit, the unreasonable design of signal line direction, width and line spacing may cause cross interference between signal transmission lines.

2. As far as possible to avoid adjacent input and output wires and long-distance parallel wiring. Biex tnaqqas il-krosstalk tal-linji tas-sinjali paralleli, l-ispazjar bejn il-linji tas-sinjali jista ‘jiżdied, jew ċinturini ta’ iżolament jistgħu jiddaħħlu bejn il-linji tas-sinjali.

3. Il-wisa ‘tal-linja fuq il-PCB għandha tkun uniformi u m’għandha sseħħ l-ebda mutazzjoni tal-wisa’ tal-linja. Il-liwja tal-wajers tal-PCB m’għandhiex tuża kantuniera ta ’90 grad, għandha tuża ark jew Angolu ta’ 135 grad, kemm jista ‘jkun biex iżżomm il-kontinwità tal-impedenza tal-linja.

4. Minimize the area of the current loop. The external radiation intensity of current-carrying circuit is proportional to the current passing through, the loop area and the square of signal frequency. Reducing the current loop area can reduce the ELECTROMAGNETIC interference of PCB.

5. As far as possible to reduce the length of the wire, increase the width of the wire, is conducive to reducing the impedance of the wire.

6. For switch control signals, the number of SIGNAL PCB wiring that changes the state at the same time should be reduced as far as possible.