Ak ogmantasyon sikwi entegre vitès chanje vitès ak Komisyon Konsèy PCB density, Signal Integrity has become one of the issues that must be concerned in high-speed digital PCB design. The parameters of components and PCB board, the layout of components on PCB board, the wiring of high-speed Signal line and other factors, Can cause problems with signal integrity.

For PCB layouts, signal integrity requires a board layout that does not affect signal timing or voltage, while for circuit wiring, signal integrity requires termination elements, layout strategies, and wiring information. Gwo vitès siyal sou yon PCB, move plasman nan eleman fen, oswa fil elektrik kòrèk nan siyal gwo vitès ka lakòz pwoblèm entegrite siyal, ki ka lakòz sistèm nan pwodiksyon done kòrèk, kous la travay mal oswa pa travay nan tout. How to take signal integrity into full consideration and take effective control measures in PCB design has become a hot topic in PCB design industry.

Signal integrity Problem Good signal integrity means that the signal can respond with the correct timing and voltage level values when required. Kontrèman, lè siyal la pa reponn byen, gen yon pwoblèm entegrite siyal. Signal integrity problems can lead to or directly lead to signal distortion, timing errors, incorrect data, address and control lines, and system misoperation, or even system crash. Nan pwosesis la nan pratik konsepsyon PCB, moun yo te akimile yon anpil nan règ konsepsyon PCB. In PCB design, the signal integrity of PCB can be better achieved by carefully referring to these design rules.

When designing PCB, we should first understand the design information of the whole circuit board, which mainly includes:

1. The number of devices, device size, device package, chip rate, whether PCB is divided into low speed, medium speed and high speed area, which is the interface input and output area;

2. The overall layout requirements, device layout location, whether there is a high power device, chip device heat dissipation special requirements;

3. Kalite liy siyal, vitès ak direksyon transmisyon, kondisyon kontwòl enpedans nan liy siyal, direksyon vitès otobis la ak sitiyasyon kondwi, siyal kle ak mezi pwoteksyon;

4. Kalite ekipman pou pouvwa, kalite tè, kondisyon tolerans bri pou ekipman pou pouvwa ak tè, anviwònman ak segmantasyon nan ekipman pou pouvwa ak avyon tè;

5. Kalite ak pousantaj liy revèy, sous ak direksyon liy revèy, kondisyon reta revèy, kondisyon liy ki pi long.

PCB kouch konsepsyon

Apre w fin konprann enfòmasyon debaz tablo sikwi a, li nesesè pou peze kondisyon konsepsyon pri tablo sikwi a ak entegrite siyal, epi chwazi yon kantite rezonab kouch fil elektrik. At present, the circuit board has gradually developed from single layer, double layer and four layer to more multi-layer circuit board. Multi-layer PCB design can improve the reference surface of signal routing and provide backflow path for signal, which is the main measure to achieve good signal integrity. When designing PCB layering, follow the following rules:

1. The reference plane shall preferably be the ground plane. Both power supply and ground plane can be used as reference plane, and both have certain shielding function. Sepandan, efè a pwoteksyon nan avyon ekipman pou pouvwa a pi ba anpil pase sa yo ki nan avyon an tè paske nan pi wo enpedans karakteristik li yo ak pi gwo diferans potansyèl ant avyon an ekipman pou pouvwa ak nivo tè referans.

2. Digital circuit and analog circuit are layered. Kote depans konsepsyon pèmèt, li pi bon pou fè aranjman pou sikui dijital ak analòg sou kouch separe. If must want to arrange in same wiring layer, can use ditch, add earthing line, the method such as dividing line to remedy. Pouvwa ak tè analòg ak dijital dwe separe, pa janm melanje.

3. Wout siyal kle nan kouch adjasan pa travèse zòn nan segmentasyon. Signals will form a large signal loop across the region and generate strong radiation. If the signal cable must cross the area when the ground cable is divided, a single point can be connected between the ground to form a connection bridge between the two ground points, and then the cable can be routed through the connection bridge.

4. Ta dwe gen yon avyon tè relativman konplè anba sifas eleman an. Entegrite nan avyon an tè dwe konsève osi lwen ke posib pou plak la multi. Pa gen okenn liy siyal yo nòmalman pèmèt yo kouri nan avyon an tè.

5, segondè frekans, gwo vitès, revèy ak lòt liy siyal kle yo ta dwe gen avyon tè adjasan. In this way, the distance between signal line and ground line is only the distance between PCB layers, so the actual current always flows in the ground line directly below the signal line, forming the smallest signal loop area and reducing radiation.

How to design the signal of integrity PCB

PCB layout design

Kle a nan konsepsyon entegrite siyal nan tablo enprime se layout ak fil elektrik, ki se dirèkteman gen rapò ak pèfòmans nan PCB. Prior to layout, the PCB size must be determined to meet the function at the lowest possible cost. Si PCB a twò gwo ak distribye, liy transmisyon an ka trè long, sa ki lakòz ogmante enpedans, redwi rezistans bri, ak ogmante pri. If the components are placed together, heat dissipation is poor, and coupling crosstalk may occur in adjacent wiring. Se poutèt sa, layout la dwe baze sou inite fonksyonèl yo nan kous la, pandan y ap konsidere konpatibilite elektwomayetik, dissipation chalè ak faktè koòdone.

When laying out a PCB with mixed digital and analog signals, do not mix digital and analog signals. Si siyal analòg ak dijital yo dwe melanje, asire w ke ou liy vètikal pou diminye efè kwa-couplage. Yo ta dwe separe sikwi dijital, sikwi analòg, ak sikwi bri sou tablo sikwi a, epi sikwi sansib la ta dwe dirije an premye, epi yo ta dwe elimine chemen kouple ant sikwi yo. An patikilye, konsidere revèy la, reset ak entèwonp liy yo, pa paralèl liy sa yo ak liy switch aktyèl segondè yo, otreman fasil domaje pa siyal kouti elektwomayetik, sa ki lakòz reset inatandi oswa entèwonp. The overall layout should follow the following principles:

1. Layout fonksyonèl patisyon, sikwi analòg ak sikwi dijital sou PCB ta dwe gen diferan layout espasyal.

2. Dapre pwosesis la siyal sikwi pou fè aranjman pou inite yo sikwi fonksyonèl, se konsa ke siyal la koule yo kenbe menm direksyon an.

3. Take the core components of each functional circuit unit as the center, and other components are arranged around it.

4. Shorten the connection between high-frequency components as much as possible and try to reduce their distribution parameters.

5. Easily disturbed components should not be too close to each other, input and output components should be far away.

How to design the signal of integrity PCB

PCB konsepsyon fil elektrik

All signal lines should be classified before PCB wiring. First of all, clock line, sensitive signal line, and then high-speed signal line, in order to ensure that this kind of signal through the hole is enough, distribution parameters of good characteristics, and then general unimportant signal line.

Incompatible signal lines should be far away from each other and do not parallel wiring, such as digital and analog, high speed and low speed, high current and small current, high voltage and low voltage. Kab siyal sou diferan kouch yo ta dwe achemine vètikal youn ak lòt pou diminye diafonia. Aranjman an nan liy siyal yo pi byen ranje selon direksyon an koule nan siyal la. Liy siyal pwodiksyon an nan yon sikwi pa ta dwe retrase tounen nan zòn nan liy siyal opinyon. High-speed signal lines should be kept as short as possible to avoid interfering with other signal lines. Sou panèl doub la, si sa nesesè, yo ka ajoute fil tè izolasyon sou toude bò liy siyal gwo vitès an. Tout liy revèy gwo vitès sou tablo multikouch la ta dwe pwoteje dapre longè liy revèy yo.

Prensip jeneral pou fil elektrik yo se:

1. Osi lwen ke posib yo chwazi dansite ki ba konsepsyon fil elektrik, ak siyal fil elektrik osi lwen ke posib epesè ki konsistan, fezab nan enpedans matche. Pou sikwi rf, konsepsyon ki pa rezonab nan direksyon liy siyal, lajè ak espas liy ka lakòz entèferans kwa ant liy transmisyon siyal yo.

2. osi lwen ke posib pou evite adjasan D’ ak sortie fil elektrik ak longdistans paralèl câblage. Pou redwi crosstalk nan liy siyal paralèl, espas ki la ant liy siyal yo ka ogmante, oswa senti izolasyon yo ka mete ant liy siyal yo.

3. Lajè liy lan sou PCB dwe inifòm epi pa gen okenn mitasyon nan lajè liy ki dwe fèt. Bend fil elektrik PCB pa ta dwe sèvi ak kwen 90 degre, yo ta dwe itilize arc oswa ang 135 degre, osi lwen ke posib yo kenbe kontinwite nan enpedans liy.

4. Minimize the area of the current loop. The external radiation intensity of current-carrying circuit is proportional to the current passing through, the loop area and the square of signal frequency. Reducing the current loop area can reduce the ELECTROMAGNETIC interference of PCB.

5. Osi lwen ke posib diminye longè fil la, ogmante lajè fil la, se fezab diminye enpedans fil la.

6. For switch control signals, the number of SIGNAL PCB wiring that changes the state at the same time should be reduced as far as possible.