de PCB tabula, many friends will think that it can be seen everywhere around us, from all household appliances, all kinds of accessories in the computer, to all kinds of digital products, as long as electronic products almost all use PCB board, so what is PCB board? A PCB is a PrintedCircuitBlock, which is a printed circuit board for electronic components to be inserted. A copperplated base plate is printed and etched out of the etching circuit.

Tabula PCB dividi potest in tabulam unam tabulam stratam, tabula duplicata et tabula strati multi. Partes electronicae in PCB integrantur. In fundamentali unius iacuit PCB, membra in unam partem contrahuntur, et fila in alteram conducunt. Excavant igitur tabulam ut fibulae per tabulam in alteram partem perveniant, ita fibulae partium in alteram partem iuncta sunt. Because of this, the positive and negative sides of such PCB are respectively called ComponentSide and SolderSide.

A double-layer board can be seen as two single-layer boards glued together, with electronic components and wiring on both sides of the board. Aliquando necesse est unum filum ab uno latere ad alteram partem tabulae per foramen iungi (via). Duc foramina parva foramina in PCB referta vel metallo obducta quae filis utrinque coniungi possunt. Multis iam matribus computatoriis 4 vel etiam 6 stratis PCB tabulae utuntur, cum chartae graphicae plerumque VI laminis PCB tabulae utantur. Multae altae tabulae graphicae chartulae sicut nVIDIAGeForce6Ti seriei utuntur 4 strata tabularum PCB, quae multi-circuitum PCB tabula appellatur. The problem of connecting lines between layers is also encountered on multi-layer PCBS, which can also be achieved through guide holes.

Quia multi-circulis PCB est, interdum duce foraminibus non opus est totam PCB penetrare. Tali duce foraminibus Buriedvias et Blindvias vocantur quia paucas stratas tantum penetrant. Blind holes connect several layers of internal PCBS to surface PCBS without penetrating the entire board. Defossa foramina tantum cum interioribus PCB coniuncta sunt, ergo lux a superficie non apparet. In multilayer PCB, tota tabulata iacuit directe cohaeret cum filo et potentia copia. Ita laminis indicamus ut Signum, Virtutem vel Terram. If the parts on the PCB require different power supplies, they usually have more than two power and wire layers. The more layers you use, the higher the cost. Of course, the use of more layers of PCB board to provide signal stability is very helpful.

Processus faciendi professionalem PCB tabulam admodum implicatam est. Accipe tabulam 4-circuli PCB pro exemplo. PCB tabulae principalis plerumque 4 stratis. Cum fabricandis, mediae duae tabulae convolvuntur, secantur, adservantur, oxidantur et respective electroplatae sunt. Quattuor strata sunt superficies componentes, stratum potentia, stratum et laminatio solida respective. Quattuor stratae tunc pressae sunt ut PCB pro tabula principali formarent. Then the holes were punched and made. Post purgationem, duae externae stratae lineae impressae sunt, aes, adsignatio, probatio, accumsan resistentia, tegumentum imprimendi. Demum, tota PCB (multis motherboards inclusa) in PCB cuiusque motherboard insculpta est, ac deinde vacuum packaging post transitum experimentum peragitur. If the copper skin is not well coated in THE process of PCB production, there will be poor adhesion phenomenon, easy to imply short circuit or capacitance effect (easy to cause interference). The holes on PCB must also be taken care of. If the hole is punched not in the middle, but on one side, it will result in uneven matching or easy contact with the power supply layer or formation in the middle, resulting in potential short-circuiting or bad grounding factors.

Copper wiring process

The first step in fabrication is to establish an online wiring between parts. We use negative transfer to express the working negative on a metal conductor. Dolum tenuem bracteae aeris in totam superficiem pandere et omnem excessum removere. Appendicis translatio alia methodo minus adhibita est, quae filum aeneum tantum ubi opus est apponat, sed hic de ea non loquimur.

Positive photoresists are made from photosensitizers that dissolve under illumination. There are many ways to treat photoresist on copper, but the most common way is to heat it and roll it over a surface containing photoresist. It can also be sprayed in liquid form, but the dry film provides higher resolution and allows for thinner wires. Cucullum iustum est exemplum ad PCB stratis faciendis. Cucullam tegentem photoresistam in PCB impedit ne aliquas areas of photoresistae exponas donec photoresista in lucem UV aperiatur. These areas, which are covered with photoresist, will become wiring. Aliae partes aeneae nudae sunt notandae post evolutionem photoresist. The etching process may involve dipping the board into the etching solvent or spraying the solvent onto the board. Fere utens utens chloride ferrico solvendo ut engraving etc. After etching, remove the remaining photoresist.

1. Wiring latitudine et vena

General width should not be less than 0.2mm (8mil)

On high density and high precision PCBS, pitch and line width are generally 0.3mm (12mil).

Cum bracteae aeris crassitudo circiter 50um est, filum latitudo 1 ~ 1.5mm (60mil) = 2A.

Locus communis plerumque est 80 mil, praesertim applicationes cum microprocessoribus.

2. Quam alta est frequentia tabulae altae celeritatis?

Cum ortus/actus casus signi temporis “3~6 temporis signum transmissionis est, signum velocitatis habetur.

Nam circuli digitalis, clavis est ad marginem proclivitas spectandi signi, tempus capit oriri et cadere;

According to a very classic book “High Speed Digtal Design” theory, the signal from 10% to 90% of the time is less than 6 times the wire delay, is high-speed signal! — — — — — scilicet! Even 8KHz square wave signals, as long as the edges are steep enough, are still high-speed signals, and transmission line theory needs to be used in wiring

3.PCB positis et layering

The four – layer plate has the following stacking sequence. Commoda et incommoda diversae laminationis infra explicantur;

Prima causa optima quattuor stratis. Because the outer layer is the stratum, it has a shielding effect on EMI. Meanwhile, the power supply layer is reliable and close to the stratum, which makes the internal resistance of the power supply smaller and achieves the best suburbs. Sed primum casu non potest poni densitas tabula secundum quid. Quia ergo prima lavacrum integritas non praestatur, et secundae tabulae signum peius est. In addition, this structure can not be used in the case of large power consumption of the whole board.

The second case is the one we usually use the most. A structura tabulae, non est aptae velocitatis digitalis ambitus designandi. It is difficult to maintain low power impedance in this structure. Take a plate 2 mm as an example: Z0=50ohm. To line width of 8mil. Copper foil thickness is 35цm. Ita iacuit signum et medium formationis est 0.14mm. The formation and power layer are 1.58mm. This greatly increases the internal resistance of the power supply. In this kind of structure, because the radiation is to the space, shielding plate is needed to reduce EMI.

In the third case, the signal line on layer S1 has the best quality. S2. Tactus protegens. But the power supply impedance is large. This board can be used when the power consumption of the whole board is high and the board is an interference source or adjacent to the interference source.

4. Impedimentum matching

Amplitudo signi voltage reflexi determinatur a fonte reflexionis coefficientis ρ S et oneris reflexionis coefficientis ρL.

ρL = (RL-z0)/(RL + Z0) and ρS = (rS-z0)/(RS + Z0)

In aequatione superiore, si RL=Z0, onus reflexionis coefficientis ρL=0. Si RS=Z0 fons-finis consideratio coefficiens ρS=0.

Quia linea transmissionis ordinaria impedimentum Z0 debet occurrere cum requisitis 50 ω 50 ω, et onus impeditio plerumque in millibus ohmarum ad decem millia ohmarum solet. Unde difficile est cognoscere impedimentum adaptare ad oneris partem. Tamen, quia signum impedimenti (output) solet esse relative parva, fere in decem ohms. Multo igitur facilius est impedimentum ad effectum deducendi ad fontem adaptare. Si resistor in fine oneris coniungitur, resistor partem signi absorbet in detrimentum transmissionis (intellectus meus). Cum TTL/CMOS vexillum 24mA agitatum electum est, eius output impedimentum circiter 13 ω est. Si linea tradenda impedimentum Z0=50 ω, accedat 33 ω principium-finis resistenti adaptans. 13 ω + 33 ω = 46 ω (circiter 50 ω, infirmi underdamping auxilii signum temporis setup)

Cum signa transmissionis aliae et excursus pellunt delecti, impedimentum adaptare possunt esse diversae. In summa celeritate logicae et circuitionis designatio, pro quibusdam significationibus clavis, ut horologii, significationibus moderandis, commendamus ut fons adaptor resistenti addatur.

Hoc modo signum coniunctum ab onere parte reflectitur, quia fons impedimenti compositus, signum reflexum non reflectitur retro.