Why are sensitive lines at PCB edges prone to ESD interference?

The system reset occurred when the grounding bench was tested using ESD contact discharge of 6KV at the grounding terminal. During the test, the Y capacitor connected to the ground terminal and the internal digital working ground was disconnected, and the test result was not significantly improved.

ESD interference enters the internal circuit of the product in various forms. For the tested products in this case, the test point is the ground point, most of the ESD interference energy will flow away from the grounding line, that is to say, ESD current does not flow directly into the internal circuit of the product, but, in the IEC61000-4-2 standard ESD test environment in this table equipment, the grounding line length in about 1m, The grounding line will produce larger lead inductance (can be used to estimate 1 u H/m), the electrostatic discharge interference occurs (figure 1 switch K) when closed, high frequency (less than 1 ns rising along the electrostatic discharge current does not make the products tested meet site zero voltage (FIG. 1 G point voltage in K is not zero when closed). This non-zero voltage at the ground terminal will further enter the internal circuit of the product. Figure 1 has given the schematic diagram of ESD interference into the PCB inside the product.

FIG. 1 Schematic diagram of ESD interference entering PCB inside the product

It can also be seen from Figure 1 that CP1 (parasitic capacitance between discharge point and GND), Cp2 (parasitic capacitance between PCB board and reference grounding floor), working ground of PCB board (GND) and electrostatic discharge gun (including grounding wire of electrostatic discharge gun) together form an interference path, and the interference current is ICM. In this interference path, the PCB board is in the middle, and the PCB is obviously disturbed by electrostatic discharge at this time. If there are other cables in the product, the interference will be more severe.

How did the interference lead to the reset of the tested product? After careful examination of the PCB of the tested product, it was found that the reset control line of the CPU in the PCB was placed on the edge of the PCB and outside the GND plane, as shown in Figure 2.

To explain why printed lines at the edge of a PCB are susceptible to interference, start with the parasitic capacitance between printed lines in the PCB and the reference ground plate. There is a parasitic capacitance between the printed line and the reference grounding plate, which will disturb the printed signal line in the PCB board. The schematic diagram of common mode interference voltage interfering the printed line in the PCB is shown in Figure 3.

Figure 3 shows that when common-mode interference (the common-mode interference voltage relative to the reference grounding floor) enters GND, an interference voltage will be generated between the printed line in the PCB board and GND. This interference voltage is related not only to the impedance between the printed line and the GND of the PCB board (Z in Figure 3) but also to the parasitic capacitance between the printed line and the reference grounding plate in the PCB.

Assuming that the impedance Z between the printed line and PCB board GND is unchanged, when the parasitic capacitance between the printed line and the reference grounding floor is larger, the interference voltage Vi between the printed line and PCB board GND is larger. This voltage is superimposed with the normal working voltage in the PCB and will directly affect the working circuit in the PCB.

FIG. 2 Actual diagram of partial PCB wiring of the tested product

FIG. 3 Common mode interference voltage interference PCB printed line schematic diagram

According to formula 1 for calculating the parasitic capacitance between the printed line and the reference grounding plate, the parasitic capacitance between the printed line and the reference grounding plate depends on the distance between the printed line and the reference grounding plate (H in Formula 1) and the equivalent area of the electric field formed between the printed line and the reference grounding plate

Obviously, for the circuit design in this case, the reset signal line in PCB is arranged on the edge of PCB board and has fallen outside the GND plane, so the reset signal line will be greatly interfered, resulting in the system reset phenomenon during ESD test.