In the process of PCB design, because the plane segmentation, may lead to a reference plane of discontinuous signal, for low frequency signal, may have nothing to do, in the high frequency digital systems, high frequency signal to the reference plane for return path, namely the flow path, if the reference ᒣ surface discontinuity, signal across the break up, this will bring many problems, Such as EMI, crosstalk and other problems. In this case, the segmentation needs to be stitched to provide a shorter backflow path for the signal. Common processing methods include adding sewing capacitance and bridge:

A. Stiching Capacitor˖

Usually, a 0402 or 0603 ceramic capacitor is placed across the signal division, and the capacitance of the capacitor is 0.01uF or 0.1uF. If the space allows, several more like capacitors ˗ can be added. Meanwhile, try to ensure that the signal line is within the sewing capacitance of 200mil. The smaller the distance is, the better ˗ and the networks at both ends of the capacitor correspond to the networks of the reference plane through which the signal passes. See the networks connected at both ends of the capacitor in Figure 1, and the two different networks highlighted in two colors:

How to make stable PCB board

B. Bridge over ˖

Common is the “signal packet ground processing” in the signal layer across the segmentation, may also be the packet of other network signal lines, this “packet ground” as thick as possible, this processing method, refer to the following figure

How to make stable PCB board

Here is a supplementary description of the common generation of cross segmentation ˖

1. The following segmentation ˖ on a single board, there may be a lot of power supplies to process, and the number of power supplies under the limited number; After comprehensive consideration, we had to operate on the power plane. Sometimes it may be a clean and clean break ˗ and sometimes it cannot avoid a lingering connection, and it may sacrifice only a less critical signal, but it must be remedied. This feeling is like walking home, suddenly dug a ditch, this is a problem, around it, a little far, may be chased by someone’s dog; Well,

Simply build a bridge, or you can go home.

So, aside from the wild metaphor, if you do a partition in a PCB, then

Check the signal line, or something could happen.

2. The above situation is not easy to ignore, and there is another situation that may be overlooked. If VIA is too dense, leading to the cutting of the plane, after all, the other via is also occupied by the space, more will give the following to occupy, resulting in ‘cutting off, this situation is not described here, the relevant introduction is more. In this case, you need to set good rules in the early stage and check them carefully in the later stage.

Clock, reset, signals over 100M and some key bus signals cannot be separated. There is at least one complete plane, preferably the GND plane.

Clock signal, high speed signal and sensitive signal forbid cross segmentation;

Differential signals must be balanced to the ground to avoid single – line – span segmentation. (Vertical cross segmentation as far as possible)

How to make stable PCB board

The high frequency return path of all signals is located directly below the signal line of the adjacent layer. Signal integrity and timing issues can be significantly reduced by placing a solid layer underneath the signal that provides a direct loop for the signal. A 0.01uF circuit capacitor should be used when the separation and crossover between the wiring and the layer is unavoidable. When loop capacitors are used, they should be placed as close as possible to the intersection of the signal line and the layer partition.