In design, layout is an important part. The quality of the layout result will directly affect the effect of the wiring, so it can be considered that a reasonable layout is the first step to a successful Pkb design. Especially the pre-layout is the process of thinking about the entire circuit board, signal flow, heat dissipation, structure and other structures. If the pre-layout fails, no amount of effort will be needed.

PCB layout design The design process flow of printed circuit boards includes schematic design, electronic component database registration, design preparation, block division, electronic component configuration, configuration confirmation, wiring and final inspection. In the process of the process, no matter which process is found to be a problem, it must be returned to the previous process for reconfirmation or correction.

Atik sa a premye prezante règ ak teknik konsepsyon PCB yo, ak Lè sa a, eksplike kijan pou konsepsyon ak enspekte Layout PCB la, ki soti nan kondisyon DFM layout la, kondisyon konsepsyon tèmik, kondisyon entegrite siyal, kondisyon EMC, anviwònman kouch ak kondisyon divizyon tè pouvwa, ak modil pouvwa. Kondisyon yo ak lòt aspè yo pral analize an detay, epi swiv editè a pou chèche konnen detay yo.

Règ konsepsyon PCB layout

1. Anba sikonstans nòmal yo, tout eleman yo ta dwe ranje sou menm sifas tablo sikwi a. Se sèlman lè konpozan wo nivo yo twò dans, yo ka enstale kèk aparèy ki gen wotè limite ak jenerasyon chalè ki ba, tankou rezistans chip, kondansateur chip, ak kondansateur chip. Chip IC, elatriye yo mete sou kouch ki pi ba a.

2. Anba site pou asire pèfòmans elektrik la, eleman yo ta dwe mete sou griy la epi yo ta dwe ranje paralèl oswa pèpandikilè youn ak lòt yo nan lòd yo dwe pwòp ak bèl. Nan sikonstans nòmal, eleman yo pa gen dwa sipèpoze; aranjman an nan eleman yo ta dwe kontra enfòmèl ant, ak eleman yo ta dwe ranje sou Layout a tout antye. Distribisyon an se inifòm ak dans.

3. The minimum distance between adjacent land patterns of different components on the circuit board should be above 1mm.

4. Distans ki soti nan kwen an nan tablo sikwi a se jeneralman pa mwens pase 2MM. Fòm ki pi bon nan tablo sikwi a se rektangilè, ak rapò aspè a se 3:2 oswa 4:3. Lè gwosè a nan tablo sikwi a pi gwo pase 200MM pa 150MM, konsidere sa tablo sikwi a ka kenbe tèt ak fòs mekanik.

PCB layout design skills

Nan konsepsyon Layout PCB la, inite yo nan tablo sikwi yo ta dwe analize, ak konsepsyon Layout yo ta dwe baze sou fonksyon an kòmanse. Lè w ap mete tout eleman nan kous la, yo ta dwe respekte prensip sa yo:

1. Fè aranjman pou pozisyon chak inite sikwi fonksyonèl dapre koule sikwi a, pou Layout la se pratik pou sikilasyon siyal, epi siyal la kenbe nan menm direksyon an otank posib [1].

2. Take the core components of each functional unit as the center and lay out around him. The components should be uniformly, integrally and compactly arranged on the PCB to minimize and shorten the leads and connections between the components.

3. Pou sikui opere nan frekans segondè, yo dwe konsidere paramèt distribisyon ant eleman yo. An jeneral sikui, konpozan yo ta dwe ranje nan paralèl otank posib, ki pa sèlman bèl, men tou, fasil pou enstale ak fasil pou pwodui an mas.

Ki jan yo desine ak enspekte Layout PCB la

1. DFM requirements for layout

1. Yo detèmine wout pi bon pwosesis la, epi yo mete tout aparèy sou tablo a.

2. The origin of the coordinates is the intersection of the left and lower extension lines of the board frame, or the lower left pad of the lower left socket.

3. The actual size of the PCB, the location of the positioning device, etc. are consistent with the process structure element map, and the device layout of the area with restricted device height requirements meets the requirements of the structure element map.

4. Pozisyon switch la rele, aparèy reset, limyè endikatè, elatriye apwopriye, ak ba manch lan pa entèfere ak aparèy ki antoure yo.

5. Ankadreman ekstèn nan tablo a gen yon radian lis nan 197mil, oswa li fèt dapre desen an gwosè estriktirèl.

6. Tablo òdinè gen 200mil bor pwosesis; bò gòch ak bò dwat backplane la gen bor pwosesis ki pi gran pase 400mil, ak bò anwo ak pi ba yo gen bor pwosesis ki pi gran pase 680mil. Plasman aparèy la pa konfli ak pozisyon ouvèti fenèt la.

7. All kinds of additional holes (ICT positioning hole 125mil, handle bar hole, elliptical hole and fiber holder hole) that need to be added are all missing and set correctly.

8. Anplasman peny aparèy la, direksyon aparèy, anplasman aparèy, bibliyotèk aparèy, elatriye ki te trete pa vag soude pran an kont kondisyon ki nan vag soude.

9. The device layout spacing meets the assembly requirements: surface mount devices are greater than 20mil, IC is greater than 80mil, and BGA is greater than 200mil.

10. Pati yo crimping yo gen plis pase 120 mils nan distans sifas eleman yo, epi pa gen okenn aparèy nan zòn nan nan pati yo sèrtir sou sifas la soude.

11. Pa gen okenn aparèy kout ant aparèy wo, epi pa gen okenn aparèy patch ak aparèy kout ak ti entèpoze yo mete nan 5mm ant aparèy ki gen yon wotè ki pi gran pase 10mm.

12. aparèy polè gen logo silkscreen polarite. Direksyon X ak Y nan menm kalite konpozan plug-in polarize yo se menm bagay la.

13. All devices are clearly marked, no P*, REF, etc. are not clearly marked.

14. Gen 3 kurseur pwezante sou sifas la ki gen aparèy SMD, ki mete yo nan yon fòm “L”. Distans ki genyen ant sant kurseur pwezante a ak kwen tablo a pi gran pase 240 mils.

15. Si ou bezwen fè pwosesis monte, yo konsidere Layout la pou fasilite pwosesis monte ak PCB ak asanble.

16. Bor yo chipped (bò nòmal) yo ta dwe ranpli pa mwayen siyon fraisage ak twou koupon pou achte. Twou koupon pou achte a se yon anile ki pa metalize, jeneralman 40 mil an dyamèt ak 16 mil soti nan kwen an.

17. The test points used for debugging have been added in the schematic diagram, and they are placed appropriately in the layout.

Dezyèmman, kondisyon yo konsepsyon tèmik nan layout la

1. Heating components and exposed components of the casing are not in close proximity to wires and heat-sensitive components, and other components should also be properly kept away.

2. The placement of the radiator takes into account the convection problem, and there is no interference of high components in the projection area of ​​the radiator, and the range is marked on the mounting surface with silk screen.

3. Layout a pran an kont chanèl yo dissipation chalè rezonab ak lis.

4. Kondansateur elektwolitik la ta dwe byen separe ak aparèy segondè-chalè a.

5. Konsidere dissipation chalè aparèy ki gen gwo pouvwa ak aparèy anba gousset la.

Twazyèmman, kondisyon yo entegrite siyal nan layout la

1. The start-end matching is close to the sending device, and the end matching is close to the receiving device.

2. Place decoupling capacitors close to related devices

3. Place crystals, crystal oscillators and clock drive chips close to related devices.

4. Gwo vitès ak ba-vitès, dijital ak analòg yo ranje separeman dapre modil.

5. Detèmine estrikti topolojik otobis la ki baze sou rezilta analiz ak simulation oswa eksperyans ki egziste deja pou asire ke kondisyon sistèm yo satisfè.

6. If it is to modify the board design, simulate the signal integrity problem reflected in the test report and give a solution.

7. The layout of the synchronous clock bus system meets the timing requirements.

Kat, kondisyon EMC

1. Inductive devices that are prone to magnetic field coupling, such as inductors, relays, and transformers, should not be placed close to each other. When there are multiple inductance coils, the direction is vertical and they are not coupled.

2. Pou evite entèferans elektwomayetik ant aparèy la sou sifas la soude nan tablo a sèl ak tablo a adjasan sèl, pa gen okenn aparèy sansib ak aparèy radyasyon fò yo ta dwe mete sou sifas la soude nan tablo a sèl.

3. The interface components are placed close to the edge of the board, and appropriate EMC protection measures have been taken (such as shielding shells, hollowing out of the power supply ground, etc.) to improve the EMC capability of the design.

4. se sikwi pwoteksyon an mete tou pre kous la koòdone, swiv prensip la nan premye pwoteksyon ak Lè sa a, filtraj.

5. Distans ki soti nan kò a pwoteksyon ak koki pwoteksyon an nan kò a pwoteksyon ak koki kouvèti pwoteksyon se plis pase 500 mils pou aparèy yo ki gen gwo pouvwa transmèt oswa patikilyèman sansib (tankou osilateur kristal, kristal, elatriye).

6. A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong devices and signals.

Five, layer setting and power supply and ground division requirements

1. Lè de kouch siyal yo dirèkteman adjasan youn ak lòt, règ fil elektrik vètikal yo dwe defini.

2. Kouch pouvwa prensipal la se adjasan ak kouch tè korespondan li yo otank posib, ak kouch pouvwa a satisfè règ 20H.

3. Each wiring layer has a complete reference plane.

4. Planch milti-kouch yo laminated ak materyèl debaz la (CORE) se simetrik pou anpeche deformation ki te koze pa distribisyon inegal nan dansite po kòb kwiv mete ak epesè asimetri nan mwayen an.

5. Epesè tablo a pa ta dwe depase 4.5mm. Pou moun ki gen yon epesè ki pi gran pase 2.5mm (backplane ki pi gran pase 3mm), teknisyen yo ta dwe konfime ke pa gen okenn pwoblèm ak pwosesis PCB, asanble, ak ekipman, ak epesè tablo PC a se 1.6mm.

6. Lè rapò a epesè-a-dyamèt nan via a pi gran pase 10: 1, li pral konfime pa manifakti a PCB.

7. The power and ground of the optical module are separated from other power and ground to reduce interference.

8. Pwosesis pouvwa a ak tè nan eleman kle satisfè kondisyon yo.

9. Lè kontwòl enpedans obligatwa, paramèt anviwònman kouch yo satisfè kondisyon yo.

Six, power module requirements

1. Layout nan pati nan ekipman pou pouvwa asire ke liy yo opinyon ak pwodiksyon yo lis epi yo pa travèse.

2. Lè tablo sèl la bay pouvwa subboard la, mete kous filtre ki koresponn lan tou pre priz pouvwa tablo sèl la ak inlet pouvwa subboard la.

Sèt, lòt kondisyon

1. Layout la pran an kont lis an jeneral nan fil elektrik la, ak koule nan done prensipal se rezonab.

2. Ajiste devwa PIN nan esklizyon an, FPGA, EPLD, chofè otobis ak lòt aparèy dapre rezilta layout yo optimize layout la.

3. Layout la pran an kont ogmantasyon apwopriye nan espas ki la nan fil elektrik la dans pou fè pou evite sitiyasyon an ke li pa ka route.

4. Si materyèl espesyal, aparèy espesyal (tankou 0.5mmBGA, elatriye), ak pwosesis espesyal yo adopte, peryòd livrezon an ak processability yo te konplètman konsidere, ak konfime pa manifaktirè PCB ak pèsonèl pwosesis.

5. Yo te konfime relasyon ki koresponn PIN nan konektè gusset la pou anpeche direksyon ak oryantasyon konektè gusset la ranvèse.

6. If there are ICT test requirements, consider the feasibility of adding ICT test points during layout, so as to avoid difficulty in adding test points during the wiring phase.

7. When a high-speed optical module is included, the layout of the optical port transceiver circuit is prioritized.

8. Apre Layout la fini, yo te bay yon desen asanble 1:1 pou pèsonèl pwojè a pou tcheke si seleksyon pake aparèy la kòrèk kont antite aparèy la.

9. Nan ouvèti fenèt la, yo te konsidere avyon enteryè a dwe retracte, epi yo te mete yon zòn entèdiksyon fil elektrik apwopriye.