In design, layout is an important part. The quality of the layout result will directly affect the effect of the wiring, so it can be considered that a reasonable layout is the first step to a successful PCB design. Especially the pre-layout is the process of thinking about the entire circuit board, signal flow, heat dissipation, structure and other structures. If the pre-layout fails, no amount of effort will be needed.

PCB layout design The design process flow of printed circuit boards includes schematic design, electronic component database registration, design preparation, block division, electronic component configuration, configuration confirmation, wiring and final inspection. In the process of the process, no matter which process is found to be a problem, it must be returned to the previous process for reconfirmation or correction.

Nkhaniyi ikufotokoza kaye malamulo ndi njira zamapangidwe a PCB, kenako ikufotokoza momwe mungapangire ndikuyang’ana masanjidwe a PCB, kuchokera pamakonzedwe a DFM a DFM, zofunikira pakupanga matenthedwe, zofunikira za umphumphu wa chizindikiro, zofunikira za EMC, zoikamo zosanjikiza ndi magawo amagetsi amagetsi, ndi ma modules amphamvu. Zofunikira ndi zina zidzawunikidwa mwatsatanetsatane, ndikutsatira mkonzi kuti mudziwe zambiri.

Malamulo a mapangidwe a PCB

1. Nthawi zonse, zigawo zonse ziyenera kukonzedwa pamtunda womwewo wa bolodi la dera. Pokhapokha pamene zigawo zapamwamba zimakhala zowuma kwambiri, zida zina zokhala ndi kutalika kochepa komanso kutentha kochepa, monga chip resistors, chip capacitors, ndi chip capacitor, zingayikidwe. Chip IC, etc. amayikidwa pamunsi wosanjikiza.

2. Pansi pa malo owonetsetsa kuti magetsi akugwira ntchito, zigawozo ziyenera kuikidwa pa gridi ndi kukonzedwa mofanana kapena perpendicular kwa wina ndi mzake kuti zikhale zabwino komanso zokongola. Muzochitika zachilendo, zigawozo siziloledwa kuti zigwirizane; makonzedwe a zigawozo ayenera kukhala ang’onoang’ono, ndipo zigawozo ziyenera kukonzedwa pa dongosolo lonse. Kugawidwa ndi yunifolomu ndi wandiweyani.

3. The minimum distance between adjacent land patterns of different components on the circuit board should be above 1mm.

4. Mtunda wochokera pamphepete mwa gulu la dera nthawi zambiri umakhala wosachepera 2MM. Mawonekedwe abwino kwambiri a board board ndi amakona anayi, ndipo mawonekedwe ake ndi 3: 2 kapena 4:3. Pamene kukula kwa bolodi la dera ndi lalikulu kuposa 200MM ndi 150MM, ganizirani zomwe gulu ladera lingathe kupirira mphamvu zamakina.

PCB layout design skills

Pamapangidwe a PCB, magawo a board board akuyenera kuwunikidwa, ndipo kapangidwe kake kayenera kutengera ntchito yoyambira. Poyala zigawo zonse za dera, mfundo zotsatirazi ziyenera kukwaniritsidwa:

1. Konzani malo a gawo lililonse logwira ntchito molingana ndi kayendedwe ka dera, kotero kuti masanjidwewo ndi osavuta kufalitsa chizindikiro, ndipo chizindikirocho chimasungidwa mofanana momwe mungathere [1].

2. Take the core components of each functional unit as the center and lay out around him. The components should be uniformly, integrally and compactly arranged on the PCB to minimize and shorten the leads and connections between the components.

3. Kwa mabwalo omwe amagwira ntchito pamtunda wapamwamba, magawo ogawa pakati pa zigawo ayenera kuganiziridwa. M’mabwalo ambiri, zigawozo ziyenera kukonzedwa mofanana momwe zingathere, zomwe sizili zokongola zokha, komanso zosavuta kuziyika komanso zosavuta kupanga.

Momwe mungapangire ndikuwunika mawonekedwe a PCB

1. DFM requirements for layout

1. Njira yabwino yopangira njira yatsimikiziridwa, ndipo zida zonse zayikidwa pa bolodi.

2. The origin of the coordinates is the intersection of the left and lower extension lines of the board frame, or the lower left pad of the lower left socket.

3. The actual size of the PCB, the location of the positioning device, etc. are consistent with the process structure element map, and the device layout of the area with restricted device height requirements meets the requirements of the structure element map.

4. Malo osinthira kuyimba, kukonzanso chipangizo, kuwala kwa chizindikiro, etc. ndi koyenera, ndipo chogwirizira sichimasokoneza zipangizo zozungulira.

5. Chojambula chakunja cha bolodi chimakhala ndi kuwala kosalala kwa 197mil, kapena kupangidwa molingana ndi zojambula za kukula kwake.

6. Ma board wamba ali ndi 200mil process m’mphepete; kumanzere ndi kumanja kwa backplane ili ndi m’mphepete mwake kuposa 400mil, ndipo kumtunda ndi kumunsi kumakhala ndi m’mphepete mwa njira zazikulu kuposa 680mil. Kuyika kwa chipangizocho sikusemphana ndi malo otsegulira zenera.

7. All kinds of additional holes (ICT positioning hole 125mil, handle bar hole, elliptical hole and fiber holder hole) that need to be added are all missing and set correctly.

8. Pini ya pini ya chipangizocho, mayendedwe a chipangizo, kukwera kwa chipangizo, laibulale ya chipangizo, ndi zina zomwe zasinthidwa ndi kutenthetsa kwamagetsi zimaganizira zofunikira za kutenthetsa kwamagetsi.

9. The device layout spacing meets the assembly requirements: surface mount devices are greater than 20mil, IC is greater than 80mil, and BGA is greater than 200mil.

10. Zigawo za crimping zili ndi mamilimita opitilira 120 pamtunda wamtunda, ndipo palibe chipangizo chomwe chili ndi gawo la crimping pamtunda.

11. Palibe zida zazifupi pakati pa zida zazitali, ndipo palibe zida zachigamba ndi zida zazifupi ndi zazing’ono zophatikizira zomwe zimayikidwa mkati mwa 5mm pakati pa zida zomwe zili ndi kutalika kopitilira 10mm.

12. Zida za polar zili ndi ma logo a polarity silkscreen. Mayendedwe a X ndi Y amtundu womwewo wa zida za polarized plug-in ndizofanana.

13. All devices are clearly marked, no P*, REF, etc. are not clearly marked.

14. Pali ma cursors oyika 3 pamwamba omwe ali ndi zida za SMD, zomwe zimayikidwa mu mawonekedwe a “L”. Mtunda pakati pa pakati pa cholozera choyikapo ndi m’mphepete mwa bolodi ndi wamkulu kuposa 240 mils.

15. Ngati mukufuna kupanga processing boarding, masanjidwe amaonedwa kuti atsogolere kukwera ndi PCB processing ndi msonkhano.

16. M’mphepete mwake (m’mphepete mwachilendo) muyenera kudzazidwa ndi mphero ndi mabowo a masitampu. Bowo la sitampu ndi lopanda zitsulo, nthawi zambiri mamilimita 40 m’mimba mwake ndi 16 ms kuchokera m’mphepete.

17. The test points used for debugging have been added in the schematic diagram, and they are placed appropriately in the layout.

Chachiwiri, zofunikira zopangira kutentha kwa kamangidwe

1. Heating components and exposed components of the casing are not in close proximity to wires and heat-sensitive components, and other components should also be properly kept away.

2. The placement of the radiator takes into account the convection problem, and there is no interference of high components in the projection area of ​​the radiator, and the range is marked on the mounting surface with silk screen.

3. Kukonzekera kumaganizira njira zomveka komanso zosalala zochepetsera kutentha.

4. The electrolytic capacitor iyenera kulekanitsidwa bwino ndi chipangizo chotentha kwambiri.

5. Ganizirani za kutentha kwa kutentha kwa zipangizo zamakono ndi zipangizo pansi pa gusset.

Chachitatu, kufunikira kwa kukhulupirika kwa chizindikirocho

1. The start-end matching is close to the sending device, and the end matching is close to the receiving device.

2. Place decoupling capacitors close to related devices

3. Place crystals, crystal oscillators and clock drive chips close to related devices.

4. Kuthamanga kwambiri komanso kutsika, digito ndi analogi zimakonzedwa mosiyana malinga ndi ma modules.

5. Dziwani mawonekedwe a topological a basi potengera kusanthula ndi zotsatira zofananira kapena zochitika zomwe zilipo kuti zitsimikizire kuti zofunikira zadongosolo zimakwaniritsidwa.

6. If it is to modify the board design, simulate the signal integrity problem reflected in the test report and give a solution.

7. The layout of the synchronous clock bus system meets the timing requirements.

Zinayi, zofunikira za EMC

1. Inductive devices that are prone to magnetic field coupling, such as inductors, relays, and transformers, should not be placed close to each other. When there are multiple inductance coils, the direction is vertical and they are not coupled.

2. Pofuna kupewa kusokoneza maginito a electromagnetic pakati pa chipangizo chowotcherera pamwamba pa bolodi limodzi ndi bolodi limodzi loyandikana, palibe zipangizo zowonongeka ndi zida zamphamvu zama radiation zomwe ziyenera kuikidwa pamtunda wa bolodi limodzi.

3. The interface components are placed close to the edge of the board, and appropriate EMC protection measures have been taken (such as shielding shells, hollowing out of the power supply ground, etc.) to improve the EMC capability of the design.

4. Dera lachitetezo limayikidwa pafupi ndi mawonekedwe a mawonekedwe, kutsatira mfundo yachitetezo choyamba ndikusefa.

5. Mtunda wochokera ku thupi lotetezera ndi chipolopolo chotchinga ku thupi lotetezera ndi chipolopolo chotchinga chotchinga ndi choposa 500 mils kwa zipangizo zomwe zili ndi mphamvu zotumizira kwambiri kapena makamaka zovuta (monga crystal oscillators, crystals, etc.).

6. A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong devices and signals.

Five, layer setting and power supply and ground division requirements

1. Pamene zigawo ziwiri za chizindikiro zili pafupi ndi wina ndi mzake, malamulo a wiring ofukula ayenera kufotokozedwa.

2. Chigawo chachikulu cha mphamvu chili pafupi ndi gawo lake lolingana ndi nthaka momwe zingathere, ndipo gawo la mphamvu limakumana ndi lamulo la 20H.

3. Each wiring layer has a complete reference plane.

4. Mipikisano wosanjikiza matabwa ndi laminated ndi core chuma (CORE) ndi symmetrical kuteteza warping chifukwa chosiyana kugawa mkuwa kachulukidwe khungu ndi asymmetrical makulidwe a sing’anga.

5. Makulidwe a bolodi sayenera kupitirira 4.5mm. Kwa iwo omwe ali ndi makulidwe akulu kuposa 2.5mm (backplane wamkulu kuposa 3mm), amisiri ayenera kutsimikizira kuti palibe vuto ndi PCB processing, msonkhano, ndi zida, ndipo makulidwe a bolodi la PC ndi 1.6mm.

6. Pamene makulidwe-ndi-m’mimba mwake chiŵerengero cha kudzera ndi wamkulu kuposa 10:1, izo kutsimikiziridwa ndi wopanga PCB.

7. The power and ground of the optical module are separated from other power and ground to reduce interference.

8. Mphamvu ndi kukonza pansi kwa zigawo zikuluzikulu zimakwaniritsa zofunikira.

9. Pamene kulamulira kwa impedance kumafunika, zigawo zoyika zosanjikiza zimakwaniritsa zofunikira.

Six, power module requirements

1. The layout of the power supply part ensures that the input and output lines are smooth and do not cross.

2. Pamene bolodi limodzi limapereka mphamvu ku bolodi laling’ono, ikani dera lofananira fyuluta pafupi ndi magetsi a bolodi limodzi ndi kulowetsa mphamvu kwa subboard.

Seven, other requirements

1. Kukonzekera kumaganizira kusalala kwa mawaya onse, ndipo mayendedwe akuluakulu a deta ndi omveka.

2. Sinthani magawo a pini a kuchotsedwa, FPGA, EPLD, dalaivala wa basi ndi zida zina molingana ndi zotsatira za masanjidwe kuti muwongolere masanjidwewo.

3. Kukonzekera kumaganizira kukula koyenera kwa danga pa waya wandiweyani kuti apewe vuto lomwe silingayendetsedwe.

4. Ngati zipangizo zapadera, zipangizo zapadera (monga 0.5mmBGA, etc.), ndi njira zapadera zimatengedwa, nthawi yobereka ndi processability zakhala zikuganiziridwa bwino, ndikutsimikiziridwa ndi opanga PCB ndi ogwira ntchito.

5. Pini yogwirizana ndi cholumikizira cha gusset yatsimikiziridwa kuti iteteze kuwongolera ndi kuwongolera kwa cholumikizira cha gusset kuti zisatembenuzidwe.

6. If there are ICT test requirements, consider the feasibility of adding ICT test points during layout, so as to avoid difficulty in adding test points during the wiring phase.

7. When a high-speed optical module is included, the layout of the optical port transceiver circuit is prioritized.

8. Pambuyo pomaliza kukonza, kujambula kwa msonkhano wa 1: 1 kwaperekedwa kwa ogwira ntchito kuti awone ngati kusankha phukusi la chipangizo kuli kolondola motsutsana ndi chipangizo cha chipangizocho.

9. Pakutsegula kwa zenera, ndege yamkati yakhala ikuganiziridwa kuti ibwezeredwa, ndipo malo oyenera oletsa mawaya aikidwa.