1. The signal line that needs to be impedance should be set in strict accordance with the line width and line distance calculated by the stack. For example, radio frequency signal (normal 50R control), important single-ended 50R, differential 90R, differential 100R and other signal lines, the specific line width and line spacing can be calculated by stacking (pictured below).

How to set the line width and line spacing in PCB Design

2. The designed line width and line spacing should consider the production process capability of the selected PCB production factory. If the line width and line spacing is set to exceed the process capability of the cooperating PCB manufacturer during the design, unnecessary production costs need to be added, and the The design cannot be produced. Generally, the line width and line spacing are controlled to 6/6mil under normal circumstances, and the via hole is 12mil (0.3mm). Basically, more than 80% of PCB manufacturers can produce it, and the production cost is the lowest. The minimum line width and line spacing is controlled to 4/4mil, and the via hole is 8mil (0.2mm). Basically, more than 70% of PCB manufacturers can produce it, but the price is slightly more expensive than the first case, not too expensive. The minimum line width and line spacing is controlled to 3.5/3.5mil, and the via hole is 8mil (0.2mm). At this time, some PCB manufacturers cannot produce it, and the price will be more expensive. The minimum line width and line spacing is controlled to 2/2mil, and the via hole is 4mil (0.1mm, at this time, it is generally HDI blind buried via design, and laser vias are required). At this time, most PCB manufacturers can’t produce it, and the price is the most expensive of. The line width and line spacing here refer to the size between elements such as line-to-hole, line-to-line, line-to-pad, line-to-via, and hole-to-disk when setting rules.

3. Regelen setzen fir den Design Flaschenhals an der Designdatei ze berücksichtegen. Wann et en 1mm BGA Chip ass, ass d’Pin Déift flaach, nëmmen eng Signallinn ass néideg tëscht den zwou Reihen vu Pins, déi op 6/6 mil gesat kënne ginn, d’Pin Déift ass méi déif, an zwou Reihen Pins sinn erfuerderlech D’Signallinn ass op 4/4mil gesat; et gëtt en 0.65 mm BGA Chip, deen allgemeng op 4/4mil gesat gëtt; et gëtt 0.5 mm BGA Chip, déi allgemeng Linn Breet an Linn Abstand muss 3.5 / 3.5mil gesat ginn; et gëtt eng 0.4mm BGA Chips allgemeng HDI Design verlaangen. Am Allgemengen, fir den Design Flaschenhals, kënnt Dir regional Reegele setzen (kuckt d’Enn vum Artikel [AD Software fir ROOM ze setzen, ALLEGRO Software fir regional Reegelen ze setzen]), déi lokal Zeilbreed an Zeilabstand op e klenge Punkt setzen, a setzen d’Regele fir aner Deeler vum PCB fir d’Produktioun méi grouss ze sinn. Verbesseren de qualifizéierten Taux vun PCB produzéiert.

4. Et muss no der Dicht vum PCB Design gesat ginn. D’Dicht ass méi kleng an de Board ass méi locker. D’Linnbreed an d’Linnabstand kënne méi grouss gesat ginn, a vice versa. D’Routine kann no de folgende Schrëtt agestallt ginn:

1) 8/8mil, 12mil (0.3mm) fir iwwer Loch.

2) 6/6mil, 12mil (0.3mm) fir iwwer Loch.

3) 4/4mil, 8mil (0.2mm) fir iwwer Loch.

4) 3.5/3.5mil, 8mil (0.2mm) fir iwwer Loch.

5) 3.5/3.5mil, 4mil fir iwwer Loch (0.1mm, Laserbohrung).

6) 2/2mil, 4mil fir iwwer Loch (0.1mm, Laserbohrung).