In design, layout is an important part. The quality of the layout result will directly affect the effect of the wiring, so it can be considered that a reasonable layout is the first step to a successful PCB design. Especially the pre-layout is the process of thinking about the entire circuit board, signal flow, heat dissipation, structure and other structures. If the pre-layout fails, no amount of effort will be needed.

PCB layout design The design process flow of printed circuit boards includes schematic design, electronic component database registration, design preparation, block division, electronic component configuration, configuration confirmation, wiring and final inspection. In the process of the process, no matter which process is found to be a problem, it must be returned to the previous process for reconfirmation or correction.

Nkan yii kọkọ ṣafihan awọn ofin apẹrẹ ipilẹ PCB ati awọn ilana, ati lẹhinna ṣalaye bi o ṣe le ṣe apẹrẹ ati ṣayẹwo ipilẹ PCB, lati awọn ibeere DFM akọkọ, awọn ibeere apẹrẹ gbona, awọn ibeere iduroṣinṣin ifihan, awọn ibeere EMC, awọn eto Layer ati awọn ibeere pipin ilẹ agbara, ati agbara modulu. Awọn ibeere ati awọn aaye miiran yoo ṣe atupale ni kikun, ki o tẹle olootu lati wa awọn alaye naa.

PCB akọkọ oniru ofin

1. Labẹ awọn ipo deede, gbogbo awọn irinše yẹ ki o wa ni idayatọ lori oju kanna ti igbimọ igbimọ. Nikan nigbati awọn ipele oke-ipele ba wa ni iponju, diẹ ninu awọn ẹrọ ti o ni iwọn giga ti o ni opin ati iran ooru kekere, gẹgẹbi awọn resistors chip, capacitors chip, and chip capacitors, le fi sori ẹrọ. Chip IC, ati be be lo ti wa ni gbe lori isalẹ Layer.

2. Labẹ ayika ile ti idaniloju iṣẹ ṣiṣe itanna, awọn paati yẹ ki o gbe sori akoj ati ṣeto ni afiwe tabi papẹndikula si ara wọn lati le jẹ afinju ati ẹwa. Labẹ awọn ipo deede, awọn paati ko gba laaye lati ni lqkan; iṣeto ti awọn paati yẹ ki o jẹ iwapọ, ati awọn paati yẹ ki o ṣeto lori gbogbo ifilelẹ naa. Pinpin jẹ aṣọ ile ati ipon.

3. The minimum distance between adjacent land patterns of different components on the circuit board should be above 1mm.

4. Awọn ijinna lati eti ti awọn Circuit ọkọ ni gbogbo ko kere ju 2MM. Apẹrẹ ti o dara julọ ti igbimọ Circuit jẹ onigun mẹrin, ati ipin ipin jẹ 3: 2 tabi 4: 3. Nigbati awọn iwọn ti awọn Circuit ọkọ ni o tobi ju 200MM nipa 150MM, ro ohun ti awọn Circuit ọkọ le withstand Mechanical agbara.

PCB layout design skills

Ninu apẹrẹ akọkọ ti PCB, awọn ẹya ti igbimọ Circuit yẹ ki o ṣe atupale, ati apẹrẹ akọkọ yẹ ki o da lori iṣẹ ibẹrẹ. Nigbati o ba ṣeto gbogbo awọn paati ti Circuit, awọn ipilẹ wọnyi yẹ ki o pade:

1. Ṣeto ipo ti ẹyọkan iṣẹ-ṣiṣe kọọkan ni ibamu si ṣiṣan iyika, ki ifilelẹ naa jẹ irọrun fun kaakiri ifihan, ati pe ifihan naa wa ni itọsọna kanna bi o ti ṣee ṣe [1].

2. Take the core components of each functional unit as the center and lay out around him. The components should be uniformly, integrally and compactly arranged on the PCB to minimize and shorten the leads and connections between the components.

3. Fun awọn iyika ti n ṣiṣẹ ni awọn igbohunsafẹfẹ giga, awọn ipinpinpin pinpin laarin awọn paati gbọdọ gbero. Ni awọn iyika gbogbogbo, awọn paati yẹ ki o ṣeto ni afiwe bi o ti ṣee ṣe, eyiti kii ṣe lẹwa nikan, ṣugbọn tun rọrun lati fi sori ẹrọ ati rọrun lati awọn ọja lọpọlọpọ.

Bi o ṣe le ṣe apẹrẹ ati ṣayẹwo ipilẹ PCB

1. DFM requirements for layout

1. Ilana ilana ti o dara julọ ti pinnu, ati gbogbo awọn ẹrọ ti a ti gbe sori ọkọ.

2. The origin of the coordinates is the intersection of the left and lower extension lines of the board frame, or the lower left pad of the lower left socket.

3. The actual size of the PCB, the location of the positioning device, etc. are consistent with the process structure element map, and the device layout of the area with restricted device height requirements meets the requirements of the structure element map.

4. Ipo ti iyipada kiakia, ẹrọ atunṣe, ina afihan, bbl jẹ deede, ati ọpa mimu ko ni dabaru pẹlu awọn ẹrọ agbegbe.

5. Awọn lode fireemu ti awọn ọkọ ni o ni a dan radian ti 197mil, tabi ti a ṣe ni ibamu si awọn igbekale iwọn iyaworan.

6. Awọn igbimọ deede ni awọn egbegbe ilana 200mil; awọn ẹgbẹ osi ati ọtun ti backplane ni awọn egbegbe ilana ti o tobi ju 400mil, ati awọn ẹgbẹ oke ati isalẹ ni awọn egbegbe ilana ti o tobi ju 680mil. Gbigbe ẹrọ ko ni rogbodiyan pẹlu ipo ṣiṣi window.

7. All kinds of additional holes (ICT positioning hole 125mil, handle bar hole, elliptical hole and fiber holder hole) that need to be added are all missing and set correctly.

8. Pipọn pin ẹrọ, itọnisọna ẹrọ, ipolowo ẹrọ, ile-ikawe ẹrọ, ati bẹbẹ lọ ti a ti ni ilọsiwaju nipasẹ igbi ti igbi ṣe akiyesi awọn ibeere ti titaja igbi.

9. The device layout spacing meets the assembly requirements: surface mount devices are greater than 20mil, IC is greater than 80mil, and BGA is greater than 200mil.

10. Awọn ẹya crimping ni diẹ sii ju 120 mils ni ijinna dada paati, ati pe ko si ẹrọ ni agbegbe ti awọn ẹya crimping lori dada alurinmorin.

11. Ko si awọn ẹrọ kukuru laarin awọn ẹrọ ti o ga, ati pe ko si awọn ẹrọ patch ati awọn ohun elo interposing kukuru ati kekere ti a gbe laarin 5mm laarin awọn ẹrọ ti o ga ju 10mm lọ.

12. Pola ẹrọ ni polarity silkscreen awọn apejuwe. Awọn itọnisọna X ati Y ti iru kanna ti awọn paati plug-in polarized jẹ kanna.

13. All devices are clearly marked, no P*, REF, etc. are not clearly marked.

14. Awọn ikọsọ ipo 3 wa lori aaye ti o ni awọn ẹrọ SMD, eyiti a gbe sinu apẹrẹ “L”. Aaye laarin aarin kọsọ ipo ati eti igbimọ jẹ tobi ju 240 mils.

15. Ti o ba nilo lati se wiwọ processing, awọn ifilelẹ ti wa ni ka lati dẹrọ awọn wiwọ ati PCB processing ati ijọ.

16. Awọn egbegbe chipped (awọn egbegbe ajeji) yẹ ki o kun ni nipasẹ awọn ọpa milling ati awọn ihò ontẹ. Iho ontẹ ni a ti kii-metallized ofo, gbogbo 40 mils ni opin ati ki o 16 mils lati eti.

17. The test points used for debugging have been added in the schematic diagram, and they are placed appropriately in the layout.

Keji, awọn ibeere apẹrẹ gbona ti ifilelẹ naa

1. Heating components and exposed components of the casing are not in close proximity to wires and heat-sensitive components, and other components should also be properly kept away.

2. The placement of the radiator takes into account the convection problem, and there is no interference of high components in the projection area of ​​the radiator, and the range is marked on the mounting surface with silk screen.

3. Awọn ifilelẹ gba sinu iroyin awọn reasonable ati ki o dan ooru wọbia awọn ikanni.

4. Agbara elekitiroti yẹ ki o ya sọtọ daradara lati ẹrọ ti o ga julọ.

5. Ṣe akiyesi ifasilẹ ooru ti awọn ẹrọ ati awọn ẹrọ ti o ga julọ labẹ gusset.

Kẹta, awọn ibeere iduroṣinṣin ifihan agbara ti ifilelẹ naa

1. The start-end matching is close to the sending device, and the end matching is close to the receiving device.

2. Place decoupling capacitors close to related devices

3. Place crystals, crystal oscillators and clock drive chips close to related devices.

4. Iyara-giga ati kekere-iyara, oni-nọmba ati afọwọṣe ti wa ni idayatọ lọtọ gẹgẹbi awọn modulu.

5. Ṣe ipinnu eto topological ti ọkọ akero ti o da lori itupalẹ ati awọn abajade simulation tabi iriri ti o wa tẹlẹ lati rii daju pe awọn ibeere eto ti pade.

6. If it is to modify the board design, simulate the signal integrity problem reflected in the test report and give a solution.

7. The layout of the synchronous clock bus system meets the timing requirements.

Mẹrin, awọn ibeere EMC

1. Inductive devices that are prone to magnetic field coupling, such as inductors, relays, and transformers, should not be placed close to each other. When there are multiple inductance coils, the direction is vertical and they are not coupled.

2. Lati yago fun kikọlu itanna laarin ẹrọ ti o wa lori dada alurinmorin ti igbimọ ẹyọkan ati igbimọ ẹyọkan ti o wa nitosi, ko si awọn ẹrọ ifura ati awọn ẹrọ itanna to lagbara yẹ ki o gbe sori dada alurinmorin ti igbimọ ẹyọkan.

3. The interface components are placed close to the edge of the board, and appropriate EMC protection measures have been taken (such as shielding shells, hollowing out of the power supply ground, etc.) to improve the EMC capability of the design.

4. Awọn Circuit Idaabobo ti wa ni gbe sunmọ awọn wiwo Circuit, awọn wọnyi ni opo ti akọkọ Idaabobo ati ki o si sisẹ.

5. Ijinna lati ara idabobo ati ikarahun idabobo si ara idabobo ati ikarahun ideri idabobo jẹ diẹ sii ju 500 mils fun awọn ẹrọ ti o ni agbara gbigbe giga tabi pataki pataki (gẹgẹbi awọn oscillators gara, awọn kirisita, bbl).

6. A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong devices and signals.

Five, layer setting and power supply and ground division requirements

1. Nigbati awọn ipele ifihan agbara meji ba wa ni isunmọ taara si ara wọn, awọn ofin wiwọn inaro gbọdọ wa ni asọye.

2. Ipilẹ agbara akọkọ ti o wa ni isunmọ si ipilẹ ilẹ ti o ni ibamu bi o ti ṣee ṣe, ati pe ipele agbara naa pade ofin 20H.

3. Each wiring layer has a complete reference plane.

4. Olona-Layer lọọgan ti wa ni laminated ati awọn mojuto ohun elo (CORE) jẹ symmetrical lati se warping ṣẹlẹ nipasẹ uneven pinpin Ejò ara iwuwo ati asymmetrical sisanra ti awọn alabọde.

5. Awọn sisanra ti ọkọ ko yẹ ki o kọja 4.5mm. Fun awọn ti o ni sisanra ti o tobi ju 2.5mm (ọkọ ofurufu ti o tobi ju 3mm lọ), awọn onimọ-ẹrọ yẹ ki o ti jẹrisi pe ko si iṣoro pẹlu sisẹ PCB, apejọ, ati ohun elo, ati sisanra igbimọ kaadi PC jẹ 1.6mm.

6. Nigbati awọn sisanra-si-rọsẹ ratio ti awọn nipasẹ jẹ tobi ju 10: 1, o yoo wa ni timo nipa PCB olupese.

7. The power and ground of the optical module are separated from other power and ground to reduce interference.

8. Agbara ati sisẹ ilẹ ti awọn paati bọtini pade awọn ibeere.

9. Nigbati o ba nilo iṣakoso ikọjujasi, awọn ipilẹ eto Layer pade awọn ibeere.

Six, power module requirements

1. The layout of the power supply part ensures that the input and output lines are smooth and do not cross.

2. Nigbati awọn nikan ọkọ ipese agbara si awọn subboard, gbe awọn ti o baamu àlẹmọ Circuit sunmọ awọn agbara iṣan ti awọn nikan ọkọ ati awọn agbawole agbara ti awọn subboard.

Meje, awọn ibeere miiran

1. Ifilelẹ naa ṣe akiyesi ifarabalẹ gbogbogbo ti onirin, ati ṣiṣan data akọkọ jẹ oye.

2. Ṣatunṣe awọn iṣẹ iyansilẹ pin ti iyasoto, FPGA, EPLD, awakọ akero ati awọn ẹrọ miiran ni ibamu si awọn abajade akọkọ lati mu iṣeto naa dara.

3. Ifilelẹ naa ṣe akiyesi ilosoke ti o yẹ ti aaye naa ni okun onirin lati yago fun ipo ti ko le ṣe ipalọlọ.

4. Ti awọn ohun elo pataki, awọn ẹrọ pataki (gẹgẹbi 0.5mmBGA, bbl), ati awọn ilana pataki ti a gba, akoko akoko ifijiṣẹ ati ilana ilana ti ni kikun ti a ti ṣe ayẹwo, ati timo nipasẹ awọn oniṣẹ PCB ati awọn oṣiṣẹ ilana.

5. Ibasepo ti o baamu pin ti asopọ gusset ti ni idaniloju lati ṣe idiwọ itọsọna ati iṣalaye ti asopọ gusset lati yi pada.

6. If there are ICT test requirements, consider the feasibility of adding ICT test points during layout, so as to avoid difficulty in adding test points during the wiring phase.

7. When a high-speed optical module is included, the layout of the optical port transceiver circuit is prioritized.

8. Lẹhin ti iṣeto naa ti pari, a ti pese iyaworan apejọ 1: 1 fun awọn oṣiṣẹ agbese lati ṣayẹwo boya aṣayan package ẹrọ jẹ pe o tọ si ohun elo ẹrọ naa.

9. Ni šiši window, ọkọ ofurufu ti inu ni a ti ro pe o ti yọkuro, ati pe a ti ṣeto agbegbe idinamọ wiwi ti o dara.