Circuit design skills PCB cov txheej txheem tsim

Cov txheej txheem tsim PCB yooj yim yog raws li hauv qab no: kev npaj ua ntej ->; PCB structure design -& GT; PCB txheej txheem – & gt; Txuas – & gt; Kev ua kom zoo dua qub thiab tshuaj ntsuam luam ntawv -> Network and DRC inspections and structural inspections – > Plate making.

First: preparation. This includes preparing component libraries and schematics. “To do good work, must first sharpen its device”, to make a good board, in addition to the principle of good design, but also draw well. Before PCB design, the component library of schematic SCH and the component library of PCB should be prepared first. Peotel libraries can be used, but in general it is difficult to find a suitable library, it is best to make your own library according to the standard size information of the selected device. In principle, make PCB component library first, and then SCH component library. PCB cov tsev qiv ntawv cov ntawv xav tau siab, nws cuam tshuam ncaj qha rau kev teeb tsa pawg thawj coj saib; SCH’s component library requirements are relatively loose, as long as attention is paid to the definition of pin attributes and the corresponding relationship with PCB components. PS: Note the hidden pins in the standard library. Tom qab ntawd yog cov qauv tsim, npaj ua PCB tsim.

Qhov thib ob: PCB tsim qauv. Hauv cov kauj ruam no, raws li lub rooj tsav xwm hauv Circuit Court loj thiab qhov chaw ua haujlwm, PCB pawg thawj coj tau kos rau hauv PCB tsim ib puag ncig, thiab cov khoom sib txuas, cov nyees khawm/hloov, ntsia hlau qhov, sib dhos qhov thiab lwm yam tau muab tso raws li qhov xav tau. And fully consider and determine the wiring area and non-wiring area (such as how much of the screw hole around the non-wiring area).

Thib peb: PCB txheej txheem. Layout is basically putting devices on a board. At this point, if all the preparatory work mentioned above is done, the network table can be generated on the schematic diagram (Design- >; CreateNetlist), thiab tom qab ntawd ntshuam lub rooj sib tham ntawm PCB daim duab (tsim-gt; LoadNets). Pom cov cuab yeej hubbub ntawm tag nrho pawg, nruab nrab ntawm tus pin thiab ya kab txuas tam sim. Koj tuaj yeem tso tawm lub cuab yeej. Kev teeb tsa dav dav yog ua raws li cov hauv paus ntsiab lus hauv qab no:

(1). According to the electrical performance reasonable partition, generally divided into: digital circuit area (that is, afraid of interference, and interference), analog circuit area

(fear of interference), power drive area (interference source);

(2). Complete the same function of the circuit, should be placed as close as possible, and adjust the components to ensure the most simple connection; At the same time, adjust the relative position between the functional blocks to make the connection between the functional blocks the most concise;

(3). Installation position and installation intensity should be considered for components with large mass; Cov cua sov yuav tsum tau sib cais los ntawm qhov ntsuas kub rhiab, thiab yog tias tsim nyog, kev ntsuas cua sov yuav tsum tau txiav txim siab;

(4). I/O drive device as close as possible to the edge of the printing plate, close to the outlet connector;

(5). Clock generator (such as: crystal oscillator or clock oscillator) should be as close as possible to the device using the clock;

6. In each integrated circuit between the power input pin and the ground, need to add a decoupling capacitor (generally using high frequency good monolithic capacitor); Lub tantalum capacitor kuj tseem tuaj yeem tso nyob ib ncig ntawm ntau qhov kev sib txuas ua ke thaum lub rooj sib tham ntawm qhov chaw nruj.

Txhua tus tswv av. Relay coil to add discharge diode (1N4148 can be);

Hnub no. Layout requirements should be balanced, dense and orderly, not top-heavy or heavy

— Special attention should be paid to the actual size (area and height) of the components and the relative position of the components when placing the components to ensure the electrical performance of the circuit board and the feasibility and convenience of production and installation. At the same time, the above principles should be reflected

Under the premise, modify the placement of devices appropriately to make them neat and beautiful. For example, the same devices should be placed neatly and in the same direction, instead of being “strewn at random”. This step concerns the difficulty of board integral figure and next wiring degree, want to spend big effort to consider so. When layout, can make preliminary wiring first to not quite affirmative place, sufficient consideration.

Plaub: txuas xov tooj. Kev xaim hluav taws xob yog txheej txheem tseem ceeb tshaj plaws hauv PCB tsim. Qhov no yuav cuam tshuam ncaj qha rau kev ua haujlwm ntawm PCB pawg thawj coj. In the process of PCB design, wiring generally has such three levels of division: the first is the distribution, which is the most basic requirement of PCB design. If the line is not cloth, get everywhere is flying line, it will be a unqualified board, can say that there is no entry. The second is the satisfaction of electrical performance. Nov yog tus txheej txheem ntsuas seb daim ntawv luam tawm Circuit board puas tsim nyog. This is after the distribution, carefully adjust the wiring, so that it can achieve the best electrical performance. Tom qab ntawd muaj kev zoo nkauj. Yog tias koj daim ntaub thaiv tau txuas nrog, kuj tsis muaj qhov cuam tshuam rau kev ua haujlwm ntawm cov khoom siv hluav taws xob, tab sis saib yav dhau los tsis txaus ntseeg, ntxiv cov xim zoo nkauj, xim zoo nkauj, uas suav tias koj cov khoom siv hluav taws xob ua tau zoo li cas, tseem raug pov tseg hauv lwm qhov muag. This brings great inconvenience to testing and maintenance. Cov xov hlau yuav tsum ua kom zoo thiab zoo ib yam, tsis hla hla yam tsis muaj txoj cai. Tag nrho cov no yuav tsum ua tiav hauv cov ntsiab lus ntawm kev ua kom ntseeg tau kev ua haujlwm hluav taws xob thiab ua tau raws li lwm cov kev xav tau ntawm tus kheej, txwv tsis pub nws yog tso tseg lub ntsiab lus. Kev thaiv yuav tsum tau ua raws li cov hauv paus ntsiab lus hauv qab no:

(1). Feem ntau, cov xov hluav taws xob thiab cov xov hluav taws xob hauv av yuav tsum tau ua ntej ua ntej kom ntseeg tau tias kev ua haujlwm hluav taws xob ntawm lub rooj tsav xwm hauv Circuit Court. Hauv qhov xwm txheej uas qhov kev tso cai, nthuav dav dav ntawm cov khoom siv hluav taws xob, cov xov hlau hauv av kom deb li deb tau, nws yog qhov zoo tshaj plaws uas cov xov hlau hauv av dav dua li cov kab hluav taws xob, lawv kev sib raug zoo yog: hauv av xaim> fais fab kab> kab teeb liab, feem ntau teeb liab kab dav yog : 0.2 ~ 0.3mm, qhov dav tshaj plaws tuaj yeem ncav cuag 0.05 ~ 0.07mm, kab hluav taws xob yog 1.2 ~ 2.5mm feem ntau. PCB ntawm digital circuit tuaj yeem siv rau hauv Circuit Court nrog cov neeg siv dav hauv av, uas yog, hauv av network. (Kev sib piv hauv av tsis tuaj yeem siv txoj hauv kev no.)

(2). In advance, wire strict requirements (such as high frequency line) for wiring, input and output side line should avoid adjacent parallel, so as not to produce reflection interference. When necessary, ground wire should be added to isolate, and the wiring of two adjacent layers should be perpendicular to each other, which is easy to produce parasitic coupling in parallel.

(3). The oscillator housing should be grounded, and the clock line should be as short as possible, and not spread all over the place. Below the clock oscillation circuit, the special high-speed logic circuit should increase the area of the ground, and should not go to other signal lines, so that the surrounding electric field tends to zero;

(4). In order to reduce the radiation of high frequency signal, 45O broken line should be used as far as possible, instead of 90O broken line. (High requirements of the line also use double arc)

(5). Any signal line should not form a loop, if unavoidable, loop should be as small as possible; Teeb liab kab hla lub qhov yuav tsum tsawg li sai tau;

6. Txoj kab tseem ceeb yuav tsum luv thiab tuab, nrog kev tiv thaiv ntawm ob sab.

Txhua tus tswv av. When the sensitive signal and noise field signal are transmitted through flat cable, the method of “ground – signal – ground wire” is used.

Hnub no. Test points should be reserved for key signals to facilitate production and maintenance testing

Pet-name ruby. After schematic diagram wiring is completed, wiring should be optimized; At the same time, after the preliminary network check and DRC check is correct, the ground wire is filled in the area without wiring, and a large area of copper layer is used as ground wire, and the unused places are connected with the ground as ground wire on the printed board. Los yog ua kom nws muaj ntau txheej pawg thawj coj saib, lub zog siv hluav taws xob, cov kab hauv av txhua qhov nyob hauv ib txheej.

— PCB wiring process requirements

(1). kab

Generally, the signal line width is 0.3mm(12mil), and the power line width is 0.77mm(30mil) or 1.27mm(50mil). Kab nrog

The distance between lines and between lines and pads should be greater than or equal to 0.33mm(13mil). In practical application, it should be considered to increase the distance when conditions permit; When the cabling density is high, it is advisable (but not recommended) to use two cables between IC pins. The width of the cables is 0.254mm(10mil), and the distance between the cables is not less than 0.254mm(10mil).

Under special circumstances, when the pin of the device is dense and the width is narrow, the line width and line spacing can be appropriately reduced.

(2). PAD (PAD)

The basic requirements of PAD and transition hole (VIA) are: the diameter of PAD is greater than 0.6mm than the diameter of hole; For example, universal pin type resistors, capacitors and integrated circuits, using disk/hole size 1.6mm/0.8mm (63mil/32mil), socket, pin and diode 1N4007, using 1.8mm/1.0mm (71mil/39mil). In practical application, it should be determined according to the size of the actual components. If conditions are available, the size of the pad can be appropriately increased. The installation aperture of the components designed on the PCB board should be about 0.2 ~ 0.4mm larger than the actual size of the pins.

(3). Through hole (VIA)

Generally 1.27mm/0.7mm(50mil/28mil);

When the wiring density is high, the hole size can be appropriately reduced, but not too small, can consider 1.0mm/0.6mm(40mil/24mil).

(4). Spacing requirements for pads, wires and through-holes

PADandVIA: ≥0.3mm (12mil)

PADandPAD: .0.3mm (12mil)

PADandTRACK: ≥0.3mm (12mil)

TRACKandTRACK: ≥0.3mm (12mil)

Thaum ntom yog siab:

PADandVIA: ≥0.254mm (10mil)

PADandPAD: .0.254mm (10mil)

PADandTRACK: ≥0.254mm (10mil)

TRACKandTRACK: ≥0.254mm (10mil)

Thib tsib: thaiv kev ua kom zoo dua thiab tshuaj ntsuam luam ntawv. “Tsis muaj qhov zoo tshaj plaws, tsuas yog zoo dua”! Tsis muaj teeb meem ntau npaum li cas koj tso rau hauv tus tsim, thaum koj ua tiav, saib nws dua, thiab koj tseem yuav xav tias koj tuaj yeem hloov pauv ntau yam. Txoj cai tsim dav dav ntawm tus ntiv tes xoo yog qhov pom kev pom zoo siv sijhawm ob zaug ntev npaum li thawj zaug thaiv. Thaum koj xav tias tsis muaj dab tsi xav tau kho, koj tuaj yeem tso tooj liab. PolygonPlane). Kev tso tooj liab feem ntau tso rau hauv av xaim (xyuam xim rau kev sib cais ntawm cov analog thiab digital hauv av), pawg thawj coj ntau tus neeg kuj tseem yuav tsum tau tso lub zog. Rau kev luam ntawv, peb yuav tsum xyuam xim kom tsis txhob raug thaiv los ntawm lub cuab yeej lossis tshem tawm los ntawm lub qhov thiab ncoo. Nyob rau tib lub sijhawm, tsim kom pom lub ntsej muag tivthaiv ntu, hauv qab ntawm lo lus yuav tsum yog daim iav ua tiav, yog li tsis txhob cuam tshuam qib.

Thib rau: kev txheeb xyuas network thiab DRC thiab kos qauv. Ua ntej tshaj plaws, ntawm qhov ua ntej uas cov txheej txheem tsim tawm raug, tsim tawm PCB cov ntaub ntawv network thiab cov ntaub ntawv sib txuas hauv network yog NETCHECK rau kev sib raug zoo ntawm lub cev, thiab kev tsim qauv tau hloov kho raws sijhawm raws li cov ntaub ntawv tso tawm kom ntseeg tau qhov tseeb ntawm kev sib txuas xov txuas Tom qab kev txheeb xyuas lub network tau dhau los raug, DRC kev tshuaj xyuas yuav ua tiav ntawm PCB tsim, thiab kev tsim qauv yuav raug hloov kho raws li cov ntaub ntawv tso tawm cov txiaj ntsig hauv lub sijhawm kom ntseeg tau tias kev ua haujlwm hluav taws xob ntawm PCB thaiv. Thaum kawg, cov txheej txheem teeb tsa txheej txheem ntawm PCB yuav tsum tau tshuaj xyuas ntxiv thiab paub tseeb.

Xya: ua phaj. It is best to have a review process before doing so.

PCB tsim yog kev sim siab ntawm kev ua haujlwm, leej twg nyob ze rau lub siab, kev paub dhau los, kev tsim qauv ntawm pawg thawj coj yog qhov zoo. Yog li kev tsim qauv yuav tsum tau ceev faj heev, ua tib zoo xav txog txhua yam ntawm txhua yam (xws li pab txhawb kev saib xyuas thiab tshuaj xyuas qhov no ntau tus neeg tsis xav txog), ua tau zoo tshaj plaws, yuav tuaj yeem tsim lub rooj tsav xwm zoo.