Awọn ọgbọn apẹrẹ Circuit PCB ilana apẹrẹ

Ilana apẹrẹ PCB gbogbogbo jẹ bi atẹle: igbaradi alakoko ->; PCB structure design -& GT; PCB akọkọ – & gt; Waya – & gt; Iṣapeye ipa ọna ati titẹ sita iboju -> Network and DRC inspections and structural inspections – > Plate making.

First: preparation. This includes preparing component libraries and schematics. “To do good work, must first sharpen its device”, to make a good board, in addition to the principle of good design, but also draw well. Before PCB design, the component library of schematic SCH and the component library of PCB should be prepared first. Peotel libraries can be used, but in general it is difficult to find a suitable library, it is best to make your own library according to the standard size information of the selected device. In principle, make PCB component library first, and then SCH component library. Awọn ibeere ikawe paati PCB ga, o ni ipa taara lori fifi sori ọkọ; Awọn ibeere ile -ikawe paati SCH jẹ alaimuṣinṣin, niwọn igba ti a ti san akiyesi si asọye awọn abuda pin ati ibatan ti o baamu pẹlu awọn paati PCB. PS: Note the hidden pins in the standard library. Lẹhinna apẹrẹ apẹrẹ, ti ṣetan lati ṣe apẹrẹ PCB.

Keji: Apẹrẹ igbekalẹ PCB. Ni igbesẹ yii, ni ibamu si iwọn igbimọ Circuit ati ipo ẹrọ, PCB tabili dada ni a fa ni agbegbe apẹrẹ PCB, ati awọn asopọ, awọn bọtini/awọn yipada, awọn iho dabaru, awọn iho apejọ ati bẹbẹ lọ ni a gbe ni ibamu si awọn ibeere ipo. And fully consider and determine the wiring area and non-wiring area (such as how much of the screw hole around the non-wiring area).

Kẹta: Eto PCB. Layout is basically putting devices on a board. At this point, if all the preparatory work mentioned above is done, the network table can be generated on the schematic diagram (Design- >; CreateNetlist), ati lẹhinna gbe tabili tabili wọle lori aworan PCB (apẹrẹ-gt; LoadNets). Wo hubbub ẹrọ ti gbogbo opoplopo soke, laarin awọn pinni ati asopọ laini fò laini. O le lẹhinna dubulẹ ẹrọ naa. Ifilelẹ gbogbogbo ni a ṣe ni ibamu si awọn ipilẹ wọnyi:

(1). According to the electrical performance reasonable partition, generally divided into: digital circuit area (that is, afraid of interference, and interference), analog circuit area

(fear of interference), power drive area (interference source);

(2). Complete the same function of the circuit, should be placed as close as possible, and adjust the components to ensure the most simple connection; At the same time, adjust the relative position between the functional blocks to make the connection between the functional blocks the most concise;

(3). Installation position and installation intensity should be considered for components with large mass; Eroja alapapo yẹ ki o ya sọtọ lati nkan ti o ni iwọn otutu, ati ti o ba jẹ dandan, o yẹ ki a gbero awọn ọna gbigbe igbona;

(4). I/O drive device as close as possible to the edge of the printing plate, close to the outlet connector;

(5). Clock generator (such as: crystal oscillator or clock oscillator) should be as close as possible to the device using the clock;

6. In each integrated circuit between the power input pin and the ground, need to add a decoupling capacitor (generally using high frequency good monolithic capacitor); Kapasito tantalum tun le gbe ni ayika ọpọlọpọ awọn iyika ti a ṣepọ nigbati aaye igbimọ Circuit naa ṣoro.

Gbogbo onile. Relay coil to add discharge diode (1N4148 can be);

Loni. Layout requirements should be balanced, dense and orderly, not top-heavy or heavy

— Special attention should be paid to the actual size (area and height) of the components and the relative position of the components when placing the components to ensure the electrical performance of the circuit board and the feasibility and convenience of production and installation. At the same time, the above principles should be reflected

Under the premise, modify the placement of devices appropriately to make them neat and beautiful. For example, the same devices should be placed neatly and in the same direction, instead of being “strewn at random”. This step concerns the difficulty of board integral figure and next wiring degree, want to spend big effort to consider so. When layout, can make preliminary wiring first to not quite affirmative place, sufficient consideration.

Ẹkẹrin: wiwakọ. Waya jẹ ilana pataki julọ ni apẹrẹ PCB. Eyi yoo kan taara iṣẹ ti igbimọ PCB. In the process of PCB design, wiring generally has such three levels of division: the first is the distribution, which is the most basic requirement of PCB design. If the line is not cloth, get everywhere is flying line, it will be a unqualified board, can say that there is no entry. The second is the satisfaction of electrical performance. Eyi jẹ boṣewa lati wiwọn boya igbimọ Circuit ti a tẹjade jẹ oṣiṣẹ. This is after the distribution, carefully adjust the wiring, so that it can achieve the best electrical performance. Nigbana ni aesthetics wa. Ti o ba ti sopọ asọ wiwu rẹ, tun ko ni aaye ti ohun ti o ni ipa lori iṣẹ ohun elo itanna, ṣugbọn wo ti o ti kọja lainidi, ṣafikun awọ, awọ didan, ti o ṣe iṣiro bi iṣẹ ohun elo itanna rẹ ṣe dara, tun jẹ idoti ni oju awọn miiran. This brings great inconvenience to testing and maintenance. Fifiranṣẹ yẹ ki o jẹ afinju ati iṣọkan, kii ṣe alailagbara laisi awọn ofin. Gbogbo awọn wọnyi yẹ ki o ṣaṣeyọri ni ipo ti aridaju iṣẹ ṣiṣe itanna ati pade awọn ibeere ẹni kọọkan miiran, bibẹẹkọ o jẹ lati kọ nkan silẹ. Waya yẹ ki o ṣee ṣe ni ibamu si awọn ipilẹ wọnyi:

(1). Ni gbogbogbo, okun agbara ati okun ilẹ yẹ ki o kọkọ kọkọ lati rii daju iṣẹ ṣiṣe itanna ti igbimọ Circuit. Ni iwọn ti ipo gba laaye, gbooro iwọn ti ipese agbara, okun ilẹ bi o ti ṣee ṣe, o dara julọ pe okun ilẹ jẹ gbooro ju laini agbara, ibatan wọn jẹ: okun ilẹ> laini agbara> laini ifihan, nigbagbogbo iwọn ila ifihan jẹ : 0.2 ~ 0.3mm, iwọn ti o kere julọ le de ọdọ 0.05 ~ 0.07mm, laini agbara jẹ 1.2 ~ 2.5mm ni gbogbogbo. PCB ti Circuit oni -nọmba kan le ṣee lo ni Circuit pẹlu awọn oludari ilẹ jakejado, iyẹn ni, nẹtiwọọki ilẹ kan. (Ilẹ analog ko ṣee lo ni ọna yii.)

(2). In advance, wire strict requirements (such as high frequency line) for wiring, input and output side line should avoid adjacent parallel, so as not to produce reflection interference. When necessary, ground wire should be added to isolate, and the wiring of two adjacent layers should be perpendicular to each other, which is easy to produce parasitic coupling in parallel.

(3). The oscillator housing should be grounded, and the clock line should be as short as possible, and not spread all over the place. Below the clock oscillation circuit, the special high-speed logic circuit should increase the area of the ground, and should not go to other signal lines, so that the surrounding electric field tends to zero;

(4). In order to reduce the radiation of high frequency signal, 45O broken line should be used as far as possible, instead of 90O broken line. (High requirements of the line also use double arc)

(5). Any signal line should not form a loop, if unavoidable, loop should be as small as possible; Laini ifihan nipasẹ iho yẹ ki o jẹ diẹ bi o ti ṣee;

6. Laini bọtini yẹ ki o jẹ kukuru ati nipọn, pẹlu aabo ni ẹgbẹ mejeeji.

Gbogbo onile. When the sensitive signal and noise field signal are transmitted through flat cable, the method of “ground – signal – ground wire” is used.

Loni. Test points should be reserved for key signals to facilitate production and maintenance testing

Pet-name ruby. After schematic diagram wiring is completed, wiring should be optimized; At the same time, after the preliminary network check and DRC check is correct, the ground wire is filled in the area without wiring, and a large area of copper layer is used as ground wire, and the unused places are connected with the ground as ground wire on the printed board. Tabi jẹ ki o jẹ igbimọ olona-fẹlẹfẹlẹ, ipese agbara, laini ilẹ kọọkan gba aaye kan.

— PCB wiring process requirements

(1). ila

Generally, the signal line width is 0.3mm(12mil), and the power line width is 0.77mm(30mil) or 1.27mm(50mil). Laini pẹlu

The distance between lines and between lines and pads should be greater than or equal to 0.33mm(13mil). In practical application, it should be considered to increase the distance when conditions permit; When the cabling density is high, it is advisable (but not recommended) to use two cables between IC pins. The width of the cables is 0.254mm(10mil), and the distance between the cables is not less than 0.254mm(10mil).

Under special circumstances, when the pin of the device is dense and the width is narrow, the line width and line spacing can be appropriately reduced.

(2). PAD (PAD)

The basic requirements of PAD and transition hole (VIA) are: the diameter of PAD is greater than 0.6mm than the diameter of hole; For example, universal pin type resistors, capacitors and integrated circuits, using disk/hole size 1.6mm/0.8mm (63mil/32mil), socket, pin and diode 1N4007, using 1.8mm/1.0mm (71mil/39mil). In practical application, it should be determined according to the size of the actual components. If conditions are available, the size of the pad can be appropriately increased. The installation aperture of the components designed on the PCB board should be about 0.2 ~ 0.4mm larger than the actual size of the pins.

(3). Through hole (VIA)

Generally 1.27mm/0.7mm(50mil/28mil);

When the wiring density is high, the hole size can be appropriately reduced, but not too small, can consider 1.0mm/0.6mm(40mil/24mil).

(4). Spacing requirements for pads, wires and through-holes

PADandVIA: ≥0.3mm (12mil)

PADandPAD: ≥0.3mm (12mil)

PADandTRACK: ≥0.3mm (12mil)

TRACKandTRACK: ≥0.3mm (12mil)

Nigbati iwuwo ga:

PADandVIA: ≥0.254mm (10mil)

PADandPAD: ≥0.254mm (10mil)

PADandTRACK: ≥0.254mm (10mil)

TRACKandTRACK: ≥0.254mm (10mil)

Karun: iṣapeye wiwakọ ati titẹ sita iboju. “Ko si ohun ti o dara julọ, nikan dara julọ”! Laibikita ipa ti o fi sinu apẹrẹ, nigbati o ba ti pari, wo lẹẹkansi, iwọ yoo tun lero pe o le yipada pupọ. Ofin apẹrẹ gbogbogbo ti atanpako ni pe wiwọ ti o dara julọ gba lẹẹmeji ni gigun bi wiwa akọkọ. Ni kete ti o ba lero pe ohunkohun ko nilo atunṣe, o le Gbe idẹ. PolygonPlane). Fifi idẹ silẹ ni gbogbo gbigbe okun waya ilẹ silẹ (san ifojusi si ipinya ti afọwọṣe ati ilẹ oni -nọmba), igbimọ multilayer tun le nilo lati fi agbara silẹ. Fun titẹ sita iboju, o yẹ ki a fiyesi si kii ṣe idiwọ nipasẹ ẹrọ tabi yọ kuro nipasẹ iho ati paadi. Ni akoko kanna, apẹrẹ lati dojuko dada paati, isalẹ ọrọ yẹ ki o jẹ sisẹ digi, ki o ma ṣe dapo ipele naa.

Ẹkẹfa: nẹtiwọọki ati DRC ṣayẹwo ati ṣayẹwo eto. Ni akọkọ, lori aaye pe apẹrẹ iṣapẹẹrẹ jẹ deede, awọn faili nẹtiwọọki PCB ti ipilẹṣẹ ati awọn faili nẹtiwọọki eto jẹ NETCHECK fun ibatan asopọ ti ara, ati pe apẹrẹ ti tunṣe ni akoko ni ibamu si awọn abajade faili ti o jade lati rii daju deede ti asopọ asopọ wiwu; Lẹhin ti iṣayẹwo nẹtiwọọki ti kọja ni deede, ayẹwo DRC yoo ṣee ṣe lori apẹrẹ PCB, ati pe apẹrẹ naa yoo ni atunṣe ni ibamu si awọn abajade faili abajade ni akoko lati rii daju iṣẹ ṣiṣe itanna ti wiwa PCB. Lakotan, eto fifi sori ẹrọ ẹrọ ti PCB yẹ ki o ṣayẹwo siwaju ati jẹrisi.

Keje: ṣiṣe awo. It is best to have a review process before doing so.

Apẹrẹ PCB jẹ idanwo ti ọkan ti iṣẹ, tani o sunmọ ọkan, iriri giga, apẹrẹ ti igbimọ dara. Nitorinaa apẹrẹ yẹ ki o ṣọra lalailopinpin, ni kikun gbero awọn ifosiwewe ti gbogbo awọn abala (bii irọrun itọju ati ayewo eyi ọpọlọpọ eniyan ko ronu), didara julọ, yoo ni anfani lati ṣe apẹrẹ igbimọ ti o dara.