Circuit design skills PCB design process

General PCB basic design process is as follows: preliminary preparation – >; PCB structure design -& GT; Hoʻonohonoho PCB – & gt; Uila – & gt; Hoʻolālā kūpono a me ka paʻi paʻi ʻana -> Network and DRC inspections and structural inspections – > Plate making.

First: preparation. This includes preparing component libraries and schematics. “To do good work, must first sharpen its device”, to make a good board, in addition to the principle of good design, but also draw well. Before PCB design, the component library of schematic SCH and the component library of PCB should be prepared first. Peotel libraries can be used, but in general it is difficult to find a suitable library, it is best to make your own library according to the standard size information of the selected device. I ke kumumanaʻo, e hana i ka waihona waihona ʻāpana PCB ma mua, a laila waihona waihona ʻĀpana. Kiʻekiʻe nā koi o ka waihona waihona PCB, pili pono ia i ka hoʻonohonoho ʻana o ka papa; SCH’s component library requirements are relatively loose, as long as attention is paid to the definition of pin attributes and the corresponding relationship with PCB components. PS: Note the hidden pins in the standard library. A laila mākaukau ka hoʻolālā hoʻolālā, mākaukau e hana i ka hoʻolālā PCB.

ʻO ka lua: hoʻolālā hoʻolālā PCB. I kēia anuu, e like me ka nui o ka papa kaapuni a me ka hoʻonohonoho ʻana o ka mīkini, ua huki ʻia ka papa PCB i ka hoʻolālā hoʻolālā PCB, a me nā mea hoʻopili, nā pihi / nā kī, nā puka ʻā, nā puka hui a pēlā aku e kau ʻia e like me nā koina hoʻonohonoho. And fully consider and determine the wiring area and non-wiring area (such as how much of the screw hole around the non-wiring area).

ʻO ke kolu: hoʻonohonoho PCB. Layout is basically putting devices on a board. At this point, if all the preparatory work mentioned above is done, the network table can be generated on the schematic diagram (Design- >; CreateNetlist), a laila lawe mai i ka papa ʻaina pūnaewele ma ka kiʻikuhi PCB (hoʻolālā-gt; LoadNets). E ʻike i ka hubbub hāmeʻa o ka puʻu holoʻokoʻa i luna, ma waena o nā pine a me ka laina lele e pili koke ana. Hiki iā ʻoe ke waiho i ka hāmeʻa. Lawe ʻia ka ʻōnaehana maʻamau e like me nā kumumanaʻo aʻe:

(1). According to the electrical performance reasonable partition, generally divided into: digital circuit area (that is, afraid of interference, and interference), analog circuit area

(fear of interference), power drive area (interference source);

(2). Complete the same function of the circuit, should be placed as close as possible, and adjust the components to ensure the most simple connection; At the same time, adjust the relative position between the functional blocks to make the connection between the functional blocks the most concise;

(3). Installation position and installation intensity should be considered for components with large mass; Pono e hoʻokaʻawale i ka mea hoʻomehana mai ka mea wela wela, a inā pono, pono e noʻonoʻo i nā ana wela

(4). I/O drive device as close as possible to the edge of the printing plate, close to the outlet connector;

(5). Clock generator (such as: crystal oscillator or clock oscillator) should be as close as possible to the device using the clock;

6. In each integrated circuit between the power input pin and the ground, need to add a decoupling capacitor (generally using high frequency good monolithic capacitor); Hiki ke kau ʻia kahi capacitor tantalum a puni i mau kaapuni hoʻohui i ka wā e paʻa ai ka papa kaapuni.

ʻO nā mea ʻona āpau. Relay coil to add discharge diode (1N4148 can be);

I kēia lā. Layout requirements should be balanced, dense and orderly, not top-heavy or heavy

— Special attention should be paid to the actual size (area and height) of the components and the relative position of the components when placing the components to ensure the electrical performance of the circuit board and the feasibility and convenience of production and installation. At the same time, the above principles should be reflected

Under the premise, modify the placement of devices appropriately to make them neat and beautiful. For example, the same devices should be placed neatly and in the same direction, instead of being “strewn at random”. This step concerns the difficulty of board integral figure and next wiring degree, want to spend big effort to consider so. When layout, can make preliminary wiring first to not quite affirmative place, sufficient consideration.

ʻEhā: uwea. ʻO ka pilina ka hana nui i ka hoʻolālā PCB. E hoʻopili pololei kēia i ka hana o ka papa PCB. I ke kaʻina hana o ka hoʻolālā PCB, aia he ʻekolu mau pae o ka hoʻokaʻawale ʻana i ka uila: ʻo ka mua ka mahele, ʻo ia ka koi nui o ka hoʻolālā PCB. If the line is not cloth, get everywhere is flying line, it will be a unqualified board, can say that there is no entry. The second is the satisfaction of electrical performance. ʻO kēia ke ana e ana inā he kūpono ka papa kaapuni pai. This is after the distribution, carefully adjust the wiring, so that it can achieve the best electrical performance. A laila aia kekahi mea hoʻonani. Inā pili kāu lole wili, ʻaʻohe hoʻi kahi e pili ai i ka hana uila uila, akā e nānā i ka wā desultorily, e hoʻohui i nā kala, nā ʻōniʻoniʻo, e helu ana pehea ka maikaʻi o kāu hana uila, e ʻōpala i ka maka o haʻi. This brings great inconvenience to testing and maintenance. Pono ke kaulike a kaulike, ʻaʻole crisscross me ka ʻole o nā lula. Pono e hoʻokō i kēia mau mea āpau i ka pōʻaiapili o ka hōʻoia ʻana i ka hana uila a me ka hoʻokō ʻana i nā koi ʻē aʻe, inā ʻaʻole ia e haʻalele i ke kumu. Pono e hoʻokō ʻia ka uila e like me nā kumumanaʻo aʻe:

(1). Ma ka laulaha, pono e hoʻohuli mua ʻia ke kaula uila a me ka kaula honua e hōʻoia i ka hana uila o ka papa kaapuni. I ka laulā e ʻae ʻia ai, hoʻonui i ka laulā o ka lako mana, uea honua a hiki i ka hiki, ʻoi aku ka maikaʻi o ka uea honua i ʻoi aku ka nui ma mua o ka laina uila, ko lākou pili: laina uea> laina uila> laina hōʻailona, ​​maʻamau ka laulā laina hōʻailona : 0.2 ~ 0.3mm, hiki i ka laulā lahilahi ke piʻi i 0.05 ~ 0.07mm, ka laina mana he 1.2 ~ 2.5mm maʻamau. The PCB of a digital circuit can be used in a circuit with wide ground conductors, that is, a ground network. (Analog ground cannot be used in this way.)

(2). In advance, wire strict requirements (such as high frequency line) for wiring, input and output side line should avoid adjacent parallel, so as not to produce reflection interference. When necessary, ground wire should be added to isolate, and the wiring of two adjacent layers should be perpendicular to each other, which is easy to produce parasitic coupling in parallel.

(3). The oscillator housing should be grounded, and the clock line should be as short as possible, and not spread all over the place. Below the clock oscillation circuit, the special high-speed logic circuit should increase the area of the ground, and should not go to other signal lines, so that the surrounding electric field tends to zero;

(4). In order to reduce the radiation of high frequency signal, 45O broken line should be used as far as possible, instead of 90O broken line. (High requirements of the line also use double arc)

(5). Any signal line should not form a loop, if unavoidable, loop should be as small as possible; ʻO ka laina hōʻailona ma o ka lua e like me ka mea liʻiliʻi;

6. Pono pōkole a mānoanoa ka laina kī, me ka pale ʻana ma nā ʻaoʻao ʻelua.

ʻO nā mea ʻona āpau. When the sensitive signal and noise field signal are transmitted through flat cable, the method of “ground – signal – ground wire” is used.

I kēia lā. Test points should be reserved for key signals to facilitate production and maintenance testing

Pet-name ruby. After schematic diagram wiring is completed, wiring should be optimized; At the same time, after the preliminary network check and DRC check is correct, the ground wire is filled in the area without wiring, and a large area of copper layer is used as ground wire, and the unused places are connected with the ground as ground wire on the printed board. A i ʻole e hoʻolilo ia i papa papa nunui, lako mana, laina laina i kēlā me kēia noho i kahi papa.

— PCB wiring process requirements

(1). laina

Generally, the signal line width is 0.3mm(12mil), and the power line width is 0.77mm(30mil) or 1.27mm(50mil). Line with

The distance between lines and between lines and pads should be greater than or equal to 0.33mm(13mil). In practical application, it should be considered to increase the distance when conditions permit; When the cabling density is high, it is advisable (but not recommended) to use two cables between IC pins. The width of the cables is 0.254mm(10mil), and the distance between the cables is not less than 0.254mm(10mil).

Under special circumstances, when the pin of the device is dense and the width is narrow, the line width and line spacing can be appropriately reduced.

(2). PAD (PAD)

The basic requirements of PAD and transition hole (VIA) are: the diameter of PAD is greater than 0.6mm than the diameter of hole; For example, universal pin type resistors, capacitors and integrated circuits, using disk/hole size 1.6mm/0.8mm (63mil/32mil), socket, pin and diode 1N4007, using 1.8mm/1.0mm (71mil/39mil). In practical application, it should be determined according to the size of the actual components. If conditions are available, the size of the pad can be appropriately increased. The installation aperture of the components designed on the PCB board should be about 0.2 ~ 0.4mm larger than the actual size of the pins.

(3). Through hole (VIA)

Generally 1.27mm/0.7mm(50mil/28mil);

When the wiring density is high, the hole size can be appropriately reduced, but not too small, can consider 1.0mm/0.6mm(40mil/24mil).

(4). Spacing requirements for pads, wires and through-holes

PADandVIA: ≥0.3mm (12mil)

PADandPAD: ≥0.3mm (12mil)

PADandTRACK: ≥0.3mm (12mil)

TRACKandTRACK: ≥0.3mm (12mil)

Ke kiʻekiʻe ke kiʻekiʻe:

PADandVIA: ≥0.254mm (10mil)

PADandPAD: ≥0.254mm (10mil)

PADandTRACK: ≥0.254mm (10mil)

TRACKandTRACK: ≥0.254mm (10mil)

ʻO ka ʻelima: hoʻopili ʻana i ka uea a me ka paʻi paʻi ʻana. “ʻAʻohe mea maikaʻi, ʻoi aku ka maikaʻi”! He mea ʻole ka nui o ka hoʻāʻo e hoʻokomo ai i ka hoʻolālā, ke pau ʻoe, e nānā hou aku, a manaʻo ʻoe hiki iā ʻoe ke loli nui. ʻO kahi rula hoʻolālā maʻamau o ka manamana lima ʻoi aku ka lōʻihi o ka hoʻopili pono ʻana i ʻelua manawa ka lōʻihi o ka hoʻopili mua ʻana. Ke manaʻo ʻoe ʻaʻohe mea e pono ke hoʻoponopono, hiki iā ʻoe ke kau i ke keleawe. PolygonPlane). Ke waiho nei ke keleawe i ka uea lepo (hoʻolohe i ka hoʻokaʻawale ʻana o ka honua analog a me ka uila), pono paha i ka papa multilayer e kau i ka mana. No ka paʻi paʻi ʻana, pono mākou e hoʻolohe e pale ʻole ʻia e ka hāmeʻa a lawe ʻia e ka puka a me ka pale. I ka manawa like, hoʻolālā e alo i ka ʻāpana o ka ʻāpana, pono ka hana o ke aniani i lalo o ka ʻōlelo, i ʻole e huikau ka pae.

ʻEono: hōʻoia pūnaewele a me DRC a me ka nānā ʻana i ke ʻano. ʻO ka mea mua, ma ke kahua o ka pololei o ka hoʻolālā skatic, ʻo nā faila pūnaewele PCB i hana ʻia a me nā faila pūnaewele skatic he NETCHKO no ka pilina pili kino, a ua hoʻoponopono hou ʻia ka hoʻolālā e like me nā hopena o ka faila puka e hōʻoia i ka pololei o ka pilina pilina pilina. Ma hope o ka hala pololei ʻana o ka nānā pūnaewele, e hoʻokō ʻia ka hōʻoia DRC ma ka hoʻolālā PCB, a e hoʻololi ʻia ka hoʻolālā e like me nā hopena o ka faila puka i ka manawa e hōʻoia i ka hana uila o PCB uea. ʻO ka mea hope loa, pono e nānā hou a hoʻopaʻa ʻia ka ʻōnaehana hoʻonohonoho mechanical o PCB.

ʻEhiku: hana ʻana i ka pā. It is best to have a review process before doing so.

ʻO ka hoʻolālā PCB kahi ho’āʻo o ka manaʻo o ka hana, ʻo wai kokoke i ka noʻonoʻo, ʻike kiʻekiʻe, maikaʻi ka hoʻolālā o ka papa. No laila e akahele pono ka hoʻolālā, e noʻonoʻo pono i nā kumu o nā ʻaoʻao āpau (e like me ka mālama ʻana i ka mālama ʻana a me ka nānā ʻana o kēia i ka nui o ka poʻe i manaʻo ʻole ʻia), ka maikaʻi, hiki ke hoʻolālā i kahi papa maikaʻi.