Circuit design skills Pkb design process

General PCB basic design process is as follows: preliminary preparation – >; PCB structure design -& GT; Layout PCB – & gt; Fil elektrik – & gt; Rout optimize ak enprime ekran -> Network and DRC inspections and structural inspections – > Plate making.

First: preparation. This includes preparing component libraries and schematics. “To do good work, must first sharpen its device”, to make a good board, in addition to the principle of good design, but also draw well. Before PCB design, the component library of schematic SCH and the component library of PCB should be prepared first. Peotel libraries can be used, but in general it is difficult to find a suitable library, it is best to make your own library according to the standard size information of the selected device. Nan prensip, fè PCB bibliyotèk eleman an premye, ak Lè sa a, SCH bibliyotèk eleman. Kondisyon bibliyotèk eleman PCB yo wo anpil, li afekte dirèkteman sou enstalasyon tablo a; SCH’s component library requirements are relatively loose, as long as attention is paid to the definition of pin attributes and the corresponding relationship with PCB components. PS: Note the hidden pins in the standard library. Lè sa a, se konsepsyon an schematic, pare fè konsepsyon PCB.

Dezyèm: konsepsyon estriktirèl PCB. Nan etap sa a, dapre gwosè tablo sikwi a ak pwezantasyon mekanik, sifas tablo PCB la trase nan anviwònman konsepsyon PCB, ak konektè, bouton / switch, twou vis, twou asanble ak sou sa yo mete selon kondisyon pwezante. And fully consider and determine the wiring area and non-wiring area (such as how much of the screw hole around the non-wiring area).

Twazyèm: Layout PCB. Layout is basically putting devices on a board. At this point, if all the preparatory work mentioned above is done, the network table can be generated on the schematic diagram (Design- >; CreateNetlist), ak Lè sa a, enpòte tab la rezo sou dyagram PCB (konsepsyon-gt; LoadNets). Gade brouyar aparèy la nan tout pil la, ant broch yo ak koneksyon liy èd memwa. Ou ka Lè sa a, mete deyò aparèy la. Layout jeneral la te pote soti selon prensip sa yo:

. (1) According to the electrical performance reasonable partition, generally divided into: digital circuit area (that is, afraid of interference, and interference), analog circuit area

(fear of interference), power drive area (interference source);

. (2) Complete the same function of the circuit, should be placed as close as possible, and adjust the components to ensure the most simple connection; At the same time, adjust the relative position between the functional blocks to make the connection between the functional blocks the most concise;

. (3) Installation position and installation intensity should be considered for components with large mass; Eleman chofaj la ta dwe separe de eleman sansib tanperati a, epi si sa nesesè, yo ta dwe konsidere mezi konveksyon tèmik;

. (4) I/O drive device as close as possible to the edge of the printing plate, close to the outlet connector;

. (5) Clock generator (such as: crystal oscillator or clock oscillator) should be as close as possible to the device using the clock;

6. In each integrated circuit between the power input pin and the ground, need to add a decoupling capacitor (generally using high frequency good monolithic capacitor); Yon kondansateur Tantal kapab tou mete alantou plizyè sikwi entegre lè espas tablo sikwi a sere.

Tout mèt tè. Relay coil to add discharge diode (1N4148 can be);

Jodi a. Layout requirements should be balanced, dense and orderly, not top-heavy or heavy

— Special attention should be paid to the actual size (area and height) of the components and the relative position of the components when placing the components to ensure the electrical performance of the circuit board and the feasibility and convenience of production and installation. At the same time, the above principles should be reflected

Under the premise, modify the placement of devices appropriately to make them neat and beautiful. For example, the same devices should be placed neatly and in the same direction, instead of being “strewn at random”. This step concerns the difficulty of board integral figure and next wiring degree, want to spend big effort to consider so. When layout, can make preliminary wiring first to not quite affirmative place, sufficient consideration.

Katriyèm: fil elektrik. Wiring se pwosesis ki pi enpòtan nan konsepsyon PCB. Sa a pral afekte dirèkteman pèfòmans nan tablo PCB. Nan pwosesis la nan konsepsyon PCB, fil elektrik jeneralman gen tankou twa nivo divizyon: premye a se distribisyon an, ki se kondisyon ki pi fondamantal nan konsepsyon PCB. If the line is not cloth, get everywhere is flying line, it will be a unqualified board, can say that there is no entry. The second is the satisfaction of electrical performance. Sa a se estanda a pou mezire si yon tablo sikwi enprime kalifye. This is after the distribution, carefully adjust the wiring, so that it can achieve the best electrical performance. Lè sa a, gen estetik. Si twal fil elektrik ou a te konekte, tou pa gen plas la ki sa ki afekte pèfòmans aparèy elektrik, men gade sot pase desultorily, ajoute kolore, klere koulè, ki kalkile ki jan pèfòmans aparèy elektrik ou se yon bon bagay, toujou dwe fatra nan lòt moun je. This brings great inconvenience to testing and maintenance. Fil elektrik yo ta dwe pwòp ak inifòm, pa krochi san règleman yo. Tout bagay sa yo ta dwe reyalize nan yon kontèks pou asire pèfòmans elektrik ak satisfè lòt kondisyon endividyèl yo, otreman li se abandone sans lan. Fil elektrik yo ta dwe te pote soti selon prensip sa yo:

. (1) An jeneral, kab pouvwa a ak kab tè a ta dwe bat premye pou asire pèfòmans elektrik tablo sikwi a. Nan sijè ki abòde lan ki kondisyon pèmèt, elaji lajè nan ekipman pou pouvwa, fil tè osi lwen ke posib, li pi bon ke fil tè se pi laj pase liy pouvwa, relasyon yo se: fil tè> liy pouvwa> liy siyal, anjeneral siyal liy lajè se : 0.2 ~ 0.3mm, lajè a mens ka rive jwenn 0.05 ~ 0.07mm, liy elektrik se 1.2 ~ 2.5mm jeneralman. The PCB of a digital circuit can be used in a circuit with wide ground conductors, that is, a ground network. (Analog ground cannot be used in this way.)

. (2) In advance, wire strict requirements (such as high frequency line) for wiring, input and output side line should avoid adjacent parallel, so as not to produce reflection interference. When necessary, ground wire should be added to isolate, and the wiring of two adjacent layers should be perpendicular to each other, which is easy to produce parasitic coupling in parallel.

. (3) The oscillator housing should be grounded, and the clock line should be as short as possible, and not spread all over the place. Below the clock oscillation circuit, the special high-speed logic circuit should increase the area of the ground, and should not go to other signal lines, so that the surrounding electric field tends to zero;

. (4) In order to reduce the radiation of high frequency signal, 45O broken line should be used as far as possible, instead of 90O broken line. (High requirements of the line also use double arc)

. (5) Any signal line should not form a loop, if unavoidable, loop should be as small as possible; Liy siyal nan twou a ta dwe tankou ti ke posib;

6. Liy kle a ta dwe kout ak epè, ak pwoteksyon sou tou de bò yo.

Tout mèt tè. When the sensitive signal and noise field signal are transmitted through flat cable, the method of “ground – signal – ground wire” is used.

Jodi a. Test points should be reserved for key signals to facilitate production and maintenance testing

Pet-name ruby. After schematic diagram wiring is completed, wiring should be optimized; At the same time, after the preliminary network check and DRC check is correct, the ground wire is filled in the area without wiring, and a large area of copper layer is used as ground wire, and the unused places are connected with the ground as ground wire on the printed board. Or make it multi-layer board, power supply, grounding line each occupy a layer.

— PCB wiring process requirements

. (1) liy

Generally, the signal line width is 0.3mm(12mil), and the power line width is 0.77mm(30mil) or 1.27mm(50mil). Liy ak

The distance between lines and between lines and pads should be greater than or equal to 0.33mm(13mil). In practical application, it should be considered to increase the distance when conditions permit; When the cabling density is high, it is advisable (but not recommended) to use two cables between IC pins. The width of the cables is 0.254mm(10mil), and the distance between the cables is not less than 0.254mm(10mil).

Under special circumstances, when the pin of the device is dense and the width is narrow, the line width and line spacing can be appropriately reduced.

. (2) PAD (PAD)

The basic requirements of PAD and transition hole (VIA) are: the diameter of PAD is greater than 0.6mm than the diameter of hole; For example, universal pin type resistors, capacitors and integrated circuits, using disk/hole size 1.6mm/0.8mm (63mil/32mil), socket, pin and diode 1N4007, using 1.8mm/1.0mm (71mil/39mil). In practical application, it should be determined according to the size of the actual components. If conditions are available, the size of the pad can be appropriately increased. The installation aperture of the components designed on the PCB board should be about 0.2 ~ 0.4mm larger than the actual size of the pins.

. (3) Through hole (VIA)

Generally 1.27mm/0.7mm(50mil/28mil);

When the wiring density is high, the hole size can be appropriately reduced, but not too small, can consider 1.0mm/0.6mm(40mil/24mil).

. (4) Spacing requirements for pads, wires and through-holes

PADandVIA: ≥0.3mm (12mil)

PADandPAD: ≥0.3mm (12mil)

PADandTRACK: ≥0.3mm (12mil)

TRACKandTRACK: ≥0.3mm (12mil)

Lè dansite a wo:

PADandVIA: ≥0.254mm (10mil)

PADandPAD: ≥0.254mm (10mil)

PADandTRACK: ≥0.254mm (10mil)

TRACKandTRACK: ≥0.254mm (10mil)

Senkyèm: optimize fil elektrik ak enprime ekran. “Pa gen okenn pi bon, sèlman pi bon”! Pa gen pwoblèm konbyen efò ou mete nan desen an, lè ou fini, gade l ‘ankò, epi ou pral toujou santi ou ka chanje anpil. Yon règ konsepsyon jeneral nan gwo pous se ke fil elektrik optimal pran de fwa osi lontan ke premye fil elektrik. Yon fwa ou santi ke pa gen anyen bezwen repare, ou ka Mete kwiv. PolygonPlane). Tap mete kòb kwiv mete jeneralman tap mete fil tè (peye atansyon sou separasyon an nan tè analòg ak dijital), tablo multi ka bezwen tou kouche pouvwa. Pou enprime ekran, nou ta dwe peye atansyon a pa dwe bloke pa aparèy la oswa retire pa twou a ak pad. An menm tan an, konsepsyon fè fas a sifas la eleman, pati anba a nan mo a yo ta dwe glas pwosesis, se konsa yo pa konfonn nivo la.

Sizyèm: rezo ak chèk DRC ak estrikti tcheke. Premyerman, sou site ke konsepsyon schematic la kòrèk, dosye rezo pwodwi PCB yo ak dosye rezo schematic yo se NETCHECK pou relasyon koneksyon fizik, epi konsepsyon an alè amande dapre rezilta dosye pwodiksyon yo pou asire ke kòrèkteman nan relasyon koneksyon fil elektrik; Aprè chèk rezo a pase kòrèkteman, chèk DRC ap fèt sou desen pkb la, epi yo pral modifye konsepsyon an selon rezilta dosye pwodiksyon an nan tan pou asire pèfòmans elektrik fil kouran pkb la. Finalman, estrikti enstalasyon mekanik PCB yo ta dwe plis tcheke ak konfime.

Setyèm: fè plak. It is best to have a review process before doing so.

Konsepsyon PCB se yon tès nan tèt ou nan travay la, ki moun ki fèmen nan tèt ou a, eksperyans segondè, desen an nan tablo a se yon bon bagay. Se konsa, konsepsyon an ta dwe pran anpil prekosyon, konplètman konsidere faktè sa yo nan tout aspè (tankou fasilite antretyen ak enspeksyon sa a yon anpil nan moun ki pa konsidere), ekselans, yo pral kapab desine yon tablo bon.