Numerous application cases of industrial, scientific, and medical radio frequency (ISM-RF) products show that the printed circuit board layout of these products is prone to various defects.People often find that the same IC installed on two different circuit boards, performance indicators will be significantly different. Variations in operating conditions, harmonic radiation, anti-interference ability, and start-up time can explain the importance of circuit board layout in a successful design.

This article lists the various design omissions, discusses the causes of each failure, and provides suggestions on how to avoid these design defects. In this paper, fr-4 dielectric, 0.0625in thickness double layer PCB as an example, the circuit board grounding. Operating in different frequency bands between 315MHz and 915MHz, Tx and Rx power between -120dbm and +13dBm.

Inductance direction

When two inductors (or even two PCB lines) are close to each other, mutual inductance will occur. The magnetic field generated by the current in the first circuit excites the current in the second circuit (Figure 1). This process is similar to the interaction between the primary and secondary coils of a transformer. When two currents interact through a magnetic field, the voltage generated is determined by mutual inductance LM:

Where, YB is the error voltage injected into circuit B, IA is the current 1 acting on circuit A. LM is very sensitive to circuit spacing, inductance loop area (i.e., magnetic flux), and loop direction. Therefore, the best balance between compact circuit layout and reduced coupling is the correct alignment of all inductors in the direction.

FIG. 1. It can be seen from magnetic field lines that mutual inductance is related to inductance alignment direction

The direction of circuit B is adjusted so that its current loop is parallel to the magnetic field line of circuit A. For this purpose, as perpendicular as possible to each other, please refer to the circuit layout of the low power FSK superheterodyne Receiver Evaluation (EV) board (MAX7042EVKIT) (Figure 2). The three inductors on the board (L3, L1 and L2) are very close to each other, and their orientation at 0°, 45° and 90° helps to reduce mutual inductance.

Figure 2. Two different PCB layouts are shown, one of which has the elements arranged in the wrong direction (L1 and L3), while the other is more suitable.

To sum up, the following principles should be followed:

The inductance spacing should be as far as possible.

Inductors are arranged at right angles to minimize crosstalk between inductors.

Lead the coupling

Just as the orientation of inductors affects magnetic coupling, so does the coupling if the leads are too close to each other. This kind of layout problem also produces what is called mutual sensation. One of the most concerned problems of RF circuit is the wiring of sensitive parts of the system, such as the input matching network, resonant channel of the receiver, antenna matching network of the transmitter, etc.

The return current path should be as close to the main current path as possible to minimize the radiation magnetic field. This arrangement helps to reduce the current loop area. The ideal low resistance path for the return current is usually the ground region below the lead — effectively limiting the loop area to a region where the thickness of the dielectric is multiplied by the length of the lead. However, if the ground region is split, the loop area increases (Figure 3). For leads passing through the split region, the return current will be forced through the high resistance path, greatly increasing the current loop area. This arrangement also makes circuit leads more susceptible to mutual inductance.

Figure 3. Complete large area grounding helps improve system performance

For an actual inductor, lead direction also has a significant effect on magnetic field coupling. If the leads of a sensitive circuit must be close to each other, it is best to align the leads vertically to reduce coupling (Figure 4). If vertical alignment is not possible, consider using a guard line. For protection wire design, please refer to the grounding and filling treatment section below.

Figure 4. Similar to Figure 1, shows the possible coupling of magnetic field lines.

To sum up, the following principles should be followed when the plate is distributed:

Complete grounding should be ensured below the lead.

Sensitive leads should be arranged vertically.

If the leads must be arranged in parallel, ensure adequate spacing or use guard wires.

Grounding via

The main problem with RF circuit layout is usually the suboptimal characteristic impedance of the circuit, including the circuit components and their interconnections. The lead with a thin copper coating is equivalent to the inductance wire and forms a distributed capacitance with other leads in the vicinity. The lead also exhibits inductance and capacitance properties as it passes through the hole.

The through-hole capacitance mainly comes from the capacitance formed between the copper cladding on the side of the through-hole pad and the copper cladding on the ground, separated by a fairly small ring. Another influence comes from the cylinder of the metal perforation itself. The effect of parasitic capacitance is generally small and usually only causes edge variation in high-speed digital signals (which is not discussed in this paper).

The biggest effect of the through-hole is the parasitic inductance caused by the corresponding interconnection mode. Because most metal perforations in RF PCB designs are the same size as lumped components, the effect of electrical perforations can be estimated using a simple formula (FIG. 5) :

Where, LVIA is lumped inductance through hole; H is the height of the throughhole, in inches; D is the diameter of the throughhole, in inches 2.

How to avoid various defects in PCB layout of printed boards

FIG. 5. PCB cross section used to estimate parasitic effects on through-hole structures

The parasitic inductance often has a great influence on the connection of bypass capacitors. Ideal bypass capacitors provide high-frequency short circuits between the supply zone and the formation, but non-ideal through-holes can affect the low-sensitivity path between the formation and the supply zone. A typical PCB through hole (d = 10 mil, h = 62.5 mil) is approximately equivalent to a 1.34nH inductor. Given the specific operating frequency of the ISM-RF product, the through-holes can adversely affect sensitive circuits such as resonant channel circuits, filters, and matching networks.

Other problems arise if sensitive circuits share holes, such as the two arms of a π – type network. For example, by placing an ideal hole equivalent to lumped inductance, the equivalent schematic is quite different from the original circuit design (FIG. 6). As with crosstalk of common current path 3, resulting in increased mutual inductance, increased crosstalk and feed-through.

How to avoid PCB design problems

Figure 6. Ideal vs. non-ideal architectures, there are potential “signal paths” in the circuit.

To sum up, circuit layout should follow the following principles:

Ensure modeling of through-hole inductance in sensitive areas.

The filter or matching network uses independent through-holes.

Note that a thinner PCB copper-clad will reduce the effect of parasitic inductance through the hole.

The length of the lead

Maxim ISM-RF product data often recommends using the shortest possible high-frequency input and output leads to minimize losses and radiation. On the other hand, such losses are usually caused by non-ideal parasitic parameters, so both parasitic inductance and capacitance affect the circuit layout, and using the shortest possible lead helps to reduce the parasitic parameters. Typically, a 10 mil wide PCB lead with a distance of 0.0625in… From a FR4 board produces an inductance of approximately 19nH/in and a distributed capacitance of approximately 1pF/in. For a LAN/ mixer circuit with a 20nH inductor and a 3pF capacitor, the effective component value will be greatly affected when the circuit and component layout are very compact.

Ipc-d-317a4 in ‘Institute for Printed Circuits’ provides an industry standard equation for estimating various impedance parameters of microstrip PCB. This document was replaced in 2003 by IPC-2251 5, which provides a more accurate calculation method for various PCB leads. Online calculators are available from a variety of sources, most of which are based on equations provided by IPC-2251. The Electromagnetic Compatibility Lab at Missouri Institute of Technology provides a very practical method for calculating PCB lead impedance 6.

The accepted criteria for calculating the impedance of microstrip lines are:

In the formula, εr is the dielectric constant of the dielectric, h is the height of the lead from the stratum, W is the lead width, and T is the lead thickness (FIG. 7). When w/h is between 0.1 and 2.0 and εr is between 1 and 15, the calculation results of this formula are quite accurate.

Figure 7. This figure is a PCB cross section (similar to Figure 5) and represents the structure used to calculate the impedance of a microstrip line.

In order to evaluate the effect of lead length, it is more practical to determine the detuning effect of ideal circuit by lead parasitical parameters. In this example, we discuss stray capacitance and inductance. The standard equation of characteristic capacitance for microstrip lines is:

Similarly, the characteristic inductance can be calculated from the equation by using the above equation:

For example, assume a PCB thickness of 0.0625in. (h = 62.5 mil), 1 ounce copper-coated lead (t = 1.35 mil), 0.01in. (w = 10 mil), and a FR-4 board. Note that the ε R of FR-4 is typically 4.35 farad /m (F/m), but can range from 4.0F/m to 4.7F/m. The eigenvalues calculated in this example are Z0 = 134 ω, C0 = 1.04pF/in, L0 = 18.7nH/in.

For AN ISM-RF design, a 12.7mm (0.5in) layout length of leads on the board can produce parasitic parameters of approximately 0.5pF and 9.3nH (Figure 8). The effect of parasitic parameters at this level on the resonant channel of the receiver (variation of LC product) may result in 315MHz ±2% or 433.92mhz ±3.5% variation. Due to the additional capacitance and inductance caused by the parasitic effect of the lead, the peak of the 315MHz oscillation frequency reaches 312.17mhz, and the peak of the 433.92mhz oscillation frequency reaches 426.6mhz.

Another example is the resonant channel of Maxim’s superheterodyne receiver (MAX7042). The recommended components are 1.2pF and 30nH at 315MHz; At 433.92MHz, it is 0pF and 16nH. Calculate the oscillation frequency of resonant circuit by using the equation:

The evaluation of the resonant circuit of the plate should include the parasitic effects of the package and the layout, and the parasitic parameters are 7.3PF and 7.5PF respectively when calculating the 315MHz resonant frequency. Note that the LC product represents lumped capacitance.

To sum up, the following principles must be followed:

Keep the lead as short as possible.

Place key circuits as close to the device as possible.

Key components are compensated according to actual layout parasitism.

Grounding and filling treatment

The grounding or power layer defines a common reference voltage that supplies power to all parts of the system through a low resistance path. Equalizing all electric fields in this way produces a good shielding mechanism.

Direct current always tends to flow along a low resistance path. In the same way, high-frequency current preferentially flows through the path with the lowest resistance. So, for a standard PCB microstrip line above the formation, the return current tries to flow into the ground region directly below the lead. As described in the lead coupling section above, the cut ground area introduces various noises that increase crosstalk either through magnetic field coupling or by converging currents (Figure 9).

How to avoid various defects in PCB layout of printed boards

FIG. 9. Keep the formation intact as much as possible, otherwise the return current will cause crosstalk.

Filled ground, also known as guard lines, is commonly used in circuits where continuous grounding is difficult to lay or where shielding sensitive circuits is required (FIG. 10). The shielding effect can be increased by placing grounding holes (i.e. hole arrays) at both ends of the lead or along the lead. 8. Do not mix the guard wire with the lead designed to provide a return current path. This arrangement can introduce crosstalk.

How to avoid various defects in PCB layout of printed boards

FIG. 10. The RF system design should avoid floating copper clad wires, especially if copper sheathing is required.

The copper-clad area is not grounded (floating) or grounded only at one end, which restricts its effectiveness. In some cases, it can cause unwanted effects by forming parasitic capacitance that changes the impedance of the surrounding wiring or creates a “latent” path between circuits. In short, if a piece of copper cladding (non-circuit signal wiring) is laid on the circuit board to ensure a consistent plating thickness. Copper-clad areas should be avoided as they affect the circuit design.

Finally, be sure to consider the effects of any ground area near the antenna. Any monopole antenna will have the ground region, wiring and holes as part of the system equilibrium, and non-ideal equilibrium wiring will affect the radiation efficiency and direction of the antenna (radiation template). Therefore, the ground area should not be placed directly below the monopole PCB lead antenna.

To sum up, the following principles should be followed:

Provide continuous and low-resistance grounding zones as far as possible.

Both ends of the filling line are grounded, and a through-hole array is used as far as possible.

Do not float copper clad wire near RF circuit, do not lay copper around RF circuit.

If the circuit board contains multiple layers, it is best to lay a ground through hole when the signal cable passes from one side to the other.

Excessive crystal capacitance

Parasitic capacitance will cause the crystal frequency to deviate from the target value 9. Therefore, some general guidelines should be followed to reduce stray capacitance of crystal pins, pads, wires, or connections to RF devices.

The following principles should be followed:

The connection between the crystal and RF device should be as short as possible.

Keep the wiring from each other as far as possible.

If the shunt parasitic capacitance is too large, remove the grounding region below the crystal.

Planar wiring inductance

Planar wiring or PCB spiral inductors are not recommended. Typical PCB manufacturing processes have certain inaccuracies, such as width and space tolerances, which greatly affect the accuracy of component values. Therefore, most controlled and high Q inductors are wound type. Secondly, you can choose multilayer ceramic inductor, multilayer chip capacitor manufacturers also provide this product. Nevertheless, some designers choose spiral inductors when they have to. The standard formula for calculating planar spiral inductance is usually Wheeler’s formula 10:

Where, a is the average radius of the coil, in inches; N is the number of turns; C is the width of the coil core (router-rinner), in inches. When the coil c “0.2a 11, the accuracy of the calculation method is within 5%.

Single-layer spiral inductors of square, hexagonal, or other shapes can be used. Very good approximations can be found to model planar inductance on integrated circuit wafers. In order to achieve this goal, the standard Wheeler formula is modified to obtain a plane inductance estimation method suitable for small size and square size 12.

Where, ρ is the filling ratio:; N is the number of turns, and dAVG is the average diameter:. For square helices, K1 = 2.36, K2 = 2.75.

There are many reasons to avoid using this type of inductor, which usually result in reduced inductance values due to space limitations. The main reasons for avoiding planar inductors are limited geometry and poor control of critical dimensions, which makes it impossible to predict inductor values. In addition, actual inductance values are difficult to control during PCB production, and inductance also tends to couple noise to other parts of the circuit.