Yadda za a guji matsalolin ƙirar PCB?

Lambobin aikace-aikace da yawa na samfuran mitar rediyo (ISM-RF) na masana’antu, kimiyya, da likita suna nuna cewa buga kewaye hukumar shimfidar waɗannan samfuran yana da alaƙa da lahani iri -iri.Mutane galibi suna gano cewa IC iri ɗaya da aka sanya akan allon kewaye daban -daban guda biyu, alamun aikin zai bambanta sosai. Variations in operating conditions, harmonic radiation, anti-interference ability, and start-up time can explain the importance of circuit board layout in a successful design.

This article lists the various design omissions, discusses the causes of each failure, and provides suggestions on how to avoid these design defects. A cikin wannan takarda, fr-4 dielectric, 0.0625in kauri PCB Layer biyu a matsayin misali, allon da’irar ƙasa. Operating in different frequency bands between 315MHz and 915MHz, Tx and Rx power between -120dbm and +13dBm.

ipcb

Hanyar Inductance

Lokacin da inductors biyu (ko ma layukan PCB guda biyu) suna kusa da juna, ƙaddamarwar juna zata faru. The magnetic field generated by the current in the first circuit excites the current in the second circuit (Figure 1). This process is similar to the interaction between the primary and secondary coils of a transformer. When two currents interact through a magnetic field, the voltage generated is determined by mutual inductance LM:

Inda, YB shine kuskuren wutar lantarki da aka sanya shi cikin da’irar B, IA shine 1 na yanzu yana aiki akan kewaye A. LM is very sensitive to circuit spacing, inductance loop area (i.e., magnetic flux), and loop direction. Therefore, the best balance between compact circuit layout and reduced coupling is the correct alignment of all inductors in the direction.

FIG. 1. It can be seen from magnetic field lines that mutual inductance is related to inductance alignment direction

The direction of circuit B is adjusted so that its current loop is parallel to the magnetic field line of circuit A. Don wannan dalili, gwargwadon iyawa da juna, da fatan za a koma zuwa tsarin da’irar ƙaramar ikon FSK superheterodyne Receiver Evaluation (EV) (MAX7042EVKIT) (Hoto 2). The three inductors on the board (L3, L1 and L2) are very close to each other, and their orientation at 0°, 45° and 90° helps to reduce mutual inductance.

Hoto 2. An nuna shimfidar PCB daban -daban guda biyu, ɗayansu yana da abubuwan da aka tsara a inda bai dace ba (L1 da L3), yayin da ɗayan ya fi dacewa.

To sum up, the following principles should be followed:

Yakamata tazarar inductance ta kasance gwargwadon iko.

An shirya masu saka ido a kusurwoyi na dama don rage taƙaddama tsakanin masu sakawa.

Jagoranci hada kai

Kamar yadda daidaitawar inductors ke shafar haɗaɗɗun maganadisu, haka ma haɗaɗɗen ke idan jagororin sun yi kusa da juna. Irin wannan matsalar shimfidar wuri kuma yana haifar da abin da ake kira jin daɗin juna. Ofaya daga cikin matsalolin da suka fi damuwa da da’irar RF shine haɗaɗɗen sassan sassa na tsarin, kamar cibiyar sadarwar da ta dace da shigarwa, tashar mai karɓar mai karɓa, eriyar da ta dace da mai watsawa, da sauransu.

The return current path should be as close to the main current path as possible to minimize the radiation magnetic field. This arrangement helps to reduce the current loop area. Kyakkyawan hanyar ƙarancin juriya don dawowar yanzu galibi yankin ƙasa da ke ƙarƙashin gubar – yana iyakance yankin madauki zuwa yankin da kaurin sinadarin ke ƙaruwa ta tsawon gubar. Koyaya, idan yankin ƙasa ya rabu, yankin madauki yana ƙaruwa (Hoto 3). For leads passing through the split region, the return current will be forced through the high resistance path, greatly increasing the current loop area. This arrangement also makes circuit leads more susceptible to mutual inductance.

Hoto 3. Cikakken shimfidar wuri mai faɗi yana taimakawa haɓaka aikin tsarin

Don ainihin inductor, jagorar jagora shima yana da babban tasiri akan haɗin filin filin magnetic. Idan jagororin da’irar mai mahimmanci dole ne su kasance kusa da juna, zai fi dacewa a daidaita jagororin a tsaye don rage haɗin gwiwa (Hoto 4). If vertical alignment is not possible, consider using a guard line. For protection wire design, please refer to the grounding and filling treatment section below.

Figure 4. Similar to Figure 1, shows the possible coupling of magnetic field lines.

To sum up, the following principles should be followed when the plate is distributed:

Complete grounding should be ensured below the lead.

Sensitive leads should be arranged vertically.

If the leads must be arranged in parallel, ensure adequate spacing or use guard wires.

Grounding via

Babban matsala tare da shimfidar kewaya RF galibi shine babban haɓakar haɓakar da’irar, gami da abubuwan kewaye da haɗe -haɗe. Gubar tare da murfin tagulla na bakin ciki daidai yake da waya ta inductance kuma tana samar da ƙarfin rarrabawa tare da sauran jagororin a kusa. Jagoran kuma yana nuna shigar da kaddarorin haɓaka yayin da yake ratsa ramin.

The through-hole capacitance mainly comes from the capacitance formed between the copper cladding on the side of the through-hole pad and the copper cladding on the ground, separated by a fairly small ring. Another influence comes from the cylinder of the metal perforation itself. Illar parasitic capacitance gaba ɗaya ƙarami ne kuma galibi yana haifar da bambancin baki a cikin siginar dijital mai sauri (wanda ba a tattauna a wannan takarda ba).

Babban tasirin ramin rami shine raunin parasitic wanda yanayin yanayin haɗin kai daidai yake haifar. Because most metal perforations in RF PCB designs are the same size as lumped components, the effect of electrical perforations can be estimated using a simple formula (FIG. 5) :

Where, LVIA is lumped inductance through hole; H is the height of the throughhole, in inches; D shine diamita na ramin, a cikin inci 2.

How to avoid various defects in PCB layout of printed boards

FIG. 5. PCB cross section used to estimate parasitic effects on through-hole structures

The parasitic inductance often has a great influence on the connection of bypass capacitors. Ingantattun masu wucewa masu ƙarfi suna ba da madaidaiciyar madaidaiciyar madaidaiciya tsakanin yankin samarwa da samuwar, amma mara kyau ta cikin ramuka na iya shafar ƙarancin ƙarancin hankali tsakanin samuwar da yankin samarwa. A typical PCB through hole (d = 10 mil, h = 62.5 mil) is approximately equivalent to a 1.34nH inductor. Given the specific operating frequency of the ISM-RF product, the through-holes can adversely affect sensitive circuits such as resonant channel circuits, filters, and matching networks.

Wasu matsalolin suna tasowa idan da’irori masu mahimmanci suna raba ramuka, kamar makamai biyu na nau’in π. Misali, ta hanyar sanya madaidaicin rami mai kama da dunkulalliyar madaidaiciya, madaidaicin makirci ya sha bamban da ƙirar da’irar asali (FIG. 6). As with crosstalk of common current path 3, resulting in increased mutual inductance, increased crosstalk and feed-through.

How to avoid PCB design problems

Hoto 6. Ideal vs. Tsarin gine-gine marasa kyau, akwai yuwuwar “hanyoyin sigina” a cikin da’irar.

To sum up, circuit layout should follow the following principles:

Ensure modeling of through-hole inductance in sensitive areas.

The filter or matching network uses independent through-holes.

Note that a thinner PCB copper-clad will reduce the effect of parasitic inductance through the hole.

Tsawon gubar

Maxim ISM-RF bayanan samfur galibi yana ba da shawarar yin amfani da gajeriyar hanyar shigar da mitar da fitarwa ke haifar da rage asara da haskakawa. A gefe guda, irin wannan asarar yawanci ana haifar da sigogin parasitic marasa dacewa, don haka duka shigarwar parasitic da capacitance suna shafar tsarin kewaye, kuma amfani da guntu mafi guntu zai taimaka wajen rage sigogin parasitic. Typically, a 10 mil wide PCB lead with a distance of 0.0625in… From a FR4 board produces an inductance of approximately 19nH/in and a distributed capacitance of approximately 1pF/in. Don kewayon LAN/ mahaɗa tare da inductor 20nH da capacitor 3pF, ƙimar kayan aikin mai tasiri zai yi tasiri sosai lokacin da kewaya da shimfidar sigogi suna da ƙima.

Ipc-d-317a4 in ‘Institute for Printed Circuits’ provides an industry standard equation for estimating various impedance parameters of microstrip PCB. An maye gurbin wannan takaddar a cikin 2003 ta IPC-2251 5, wanda ke ba da ingantacciyar hanyar ƙididdigewa ga jagororin PCB daban-daban. Online calculators are available from a variety of sources, most of which are based on equations provided by IPC-2251. The Electromagnetic Compatibility Lab at Missouri Institute of Technology provides a very practical method for calculating PCB lead impedance 6.

The accepted criteria for calculating the impedance of microstrip lines are:

A cikin dabara, εr shine madaidaiciyar madaidaiciyar madaidaiciyar wutar lantarki, h shine tsayin gubar daga stratum, W shine faɗin gubar, kuma T shine kaurin gubar (FIG. 7). Lokacin da w/h ke tsakanin 0.1 da 2.0 kuma εr yana tsakanin 1 zuwa 15, sakamakon lissafin wannan dabara daidai ne.

Figure 7. This figure is a PCB cross section (similar to Figure 5) and represents the structure used to calculate the impedance of a microstrip line.

In order to evaluate the effect of lead length, it is more practical to determine the detuning effect of ideal circuit by lead parasitical parameters. A cikin wannan misalin, zamu tattauna batattun capacitance da inductance. The standard equation of characteristic capacitance for microstrip lines is:

Hakanan, ana iya ƙididdige ƙimar halayyar daga lissafi ta amfani da lissafin da ke sama:

Misali, ɗauka kaurin PCB na 0.0625in. (h = mil 62.5), 1 oganci mai rufi na jan ƙarfe (t = 1.35 mil), 0.01in. (w = mil 10), da hukumar FR-4. Lura cewa ε R na FR-4 yawanci 4.35 farad/m (F/m), amma yana iya kewayo daga 4.0F/m zuwa 4.7F/m. Abubuwan asalin asalin da aka lissafa a cikin wannan misalin sune Z0 = 134 ω, C0 = 1.04pF/in, L0 = 18.7nH/in.

Don ƙirar ISM-RF, tsayin shimfidar shimfiɗa na 12.7mm (0.5in) a kan jirgin zai iya samar da sigogin parasitic na kusan 0.5pF da 9.3nH (Hoto 8). Sakamakon sigogi na parasitic a wannan matakin akan tashar sake kunnawa ta mai karɓa (bambancin samfurin LC) na iya haifar da 315MHz ± 2% ko 433.92mhz ± 3.5% bambancin. Dangane da ƙarin ƙarfin haɓakawa da haɓakawa ta haifar da tasirin parasitic na gubar, ƙwanƙwasawar mitar motsi na 315MHz ya kai 312.17mhz, kuma ƙwanƙwasawar mitar motsi na 433.92mhz ya kai 426.6mhz.

Another example is the resonant channel of Maxim’s superheterodyne receiver (MAX7042). The recommended components are 1.2pF and 30nH at 315MHz; At 433.92MHz, it is 0pF and 16nH. Yi lissafin mitar jujjuyawar ma’abota resonant ta amfani da lissafin:

Yakamata kimanta kewayon farantin farantin yakamata ya haɗa da tasirin parasitic na kunshin da shimfida, kuma sigogin parasitic sune 7.3PF da 7.5PF bi da bi yayin lissafin mitar mitar 315MHz. Lura cewa samfurin LC yana wakiltar ƙwanƙwasa ƙarfin.

Don taƙaitawa, dole ne a bi ƙa’idodi masu zuwa:

Tsayar da gubar a takaice.

Sanya maɓallin kewayawa kusa da na’urar kamar yadda zai yiwu.

Key components are compensated according to actual layout parasitism.

Grounding da cika magani

The grounding or power layer defines a common reference voltage that supplies power to all parts of the system through a low resistance path. Daidaita duk filayen wutar lantarki ta wannan hanya yana samar da kyakkyawan tsarin garkuwa.

Direct halin yanzu ko da yaushe o ƙarin tabbatar da ya kwarara tare da wani low juriya hanya. Hakanan, babban mitar da aka fi so yana gudana ta hanyar hanya tare da mafi ƙarancin juriya. So, for a standard PCB microstrip line above the formation, the return current tries to flow into the ground region directly below the lead. As described in the lead coupling section above, the cut ground area introduces various noises that increase crosstalk either through magnetic field coupling or by converging currents (Figure 9).

How to avoid various defects in PCB layout of printed boards

FIG. 9. Keep the formation intact as much as possible, otherwise the return current will cause crosstalk.

Filled ground, also known as guard lines, is commonly used in circuits where continuous grounding is difficult to lay or where shielding sensitive circuits is required (FIG. 10). The shielding effect can be increased by placing grounding holes (i.e. hole arrays) at both ends of the lead or along the lead. 8. Kada ku haɗa waya mai tsaro tare da gubar da aka tsara don samar da hanyar dawowa ta yanzu. Wannan tsari na iya gabatar da crosstalk.

How to avoid various defects in PCB layout of printed boards

FIG. 10. Tsarin tsarin RF yakamata ya nisanci wayoyin da ke sanye da jan ƙarfe, musamman idan ana buƙatar sheathing na jan ƙarfe.

Yankin da aka lullube da jan ƙarfe ba shi da tushe (yana iyo) ko kuma an kafa shi a ƙarshen ƙarshen, wanda ke taƙaita tasirin sa. In some cases, it can cause unwanted effects by forming parasitic capacitance that changes the impedance of the surrounding wiring or creates a “latent” path between circuits. A taƙaice, idan an ɗora wani murfin jan ƙarfe (siginar siginar da ba ta kewaye ba) akan allon da’irar don tabbatar da daidaiton kauri. Wajibi ne a guji wuraren da ke sanye da jan ƙarfe yayin da suke shafar ƙirar da’irar.

A ƙarshe, tabbatar da la’akari da tasirin kowane yanki na ƙasa kusa da eriya. Duk wani eriya na monopole zai sami yankin ƙasa, wayoyi da ramuka a matsayin wani ɓangare na ma’aunin tsarin, kuma wayoyin da ba su dace ba za su shafi tasirin radiation da shugabanci na eriya (samfuri na radiation). Therefore, the ground area should not be placed directly below the monopole PCB lead antenna.

To sum up, the following principles should be followed:

Samar da yankuna na ƙasa masu ɗorewa da ƙarancin ƙarfi gwargwadon iko.

Duka duka na layin cikawa suna da tushe, kuma ana amfani da tsarar rami ta yadda zai yiwu.

Kada ku yi iyo igiyar waya da aka lullube da tagulla kusa da da’irar RF, kar ku sanya jan ƙarfe a kusa da da’irar RF.

Idan allon kewaye yana ƙunshe da yadudduka da yawa, zai fi kyau sanya ƙasa ta rami lokacin da siginar siginar ta wuce daga wannan gefe zuwa wancan.

Wuce kima crystal capacitance

Parasitic capacitance will cause the crystal frequency to deviate from the target value 9. Sabili da haka, yakamata a bi wasu jagororin gaba ɗaya don rage madaidaicin madaurin filastik, gammaye, wayoyi, ko haɗi zuwa na’urorin RF.

The following principles should be followed:

Haɗin da ke tsakanin na’urar crystal da RF yakamata ya zama takaitacce.

Keep the wiring from each other as far as possible.

Idan shunt parasitic capacitance ya yi yawa, cire yankin da ke ƙasa a ƙasa da crystal.

Planar wiring inductance

Planar wiring or PCB spiral inductors are not recommended. Typical PCB manufacturing processes have certain inaccuracies, such as width and space tolerances, which greatly affect the accuracy of component values. Therefore, most controlled and high Q inductors are wound type. Abu na biyu, zaku iya zaɓar inductor yumɓu mai ɗimbin yawa, masana’antun masu haɗa guntu da yawa kuma suna ba da wannan samfurin. Nevertheless, some designers choose spiral inductors when they have to. The standard formula for calculating planar spiral inductance is usually Wheeler’s formula 10:

Inda, a shine matsakaicin radius na coil, a inci; N shine adadin juyawa; C is the width of the coil core (router-rinner), in inches. When the coil c “0.2a 11, the accuracy of the calculation method is within 5%.

Za’a iya amfani da inductors karkace masu faɗin faifai, murabba’i, ko wasu siffofi. Very good approximations can be found to model planar inductance on integrated circuit wafers. Don cimma wannan burin, an gyara madaidaicin tsarin Wheeler don samun hanyar kimanta shigar da jirgin sama wanda ya dace da ƙaramin girman da girman murabba’i 12.

Inda, ρ shine rabo mai cika :; N shine adadin juyawa, kuma dAVG shine matsakaicin diamita:. Don helikofta murabba’i, K1 = 2.36, K2 = 2.75.

Akwai dalilai da yawa don gujewa amfani da wannan nau’in inductor, wanda galibi yana haifar da rage ƙimar ƙima saboda ƙarancin sararin samaniya. The main reasons for avoiding planar inductors are limited geometry and poor control of critical dimensions, which makes it impossible to predict inductor values. Bugu da kari, ainihin ƙimar shigarwar yana da wahalar sarrafawa yayin samarwa PCB, kuma inductance shima yana haifar da hayaniya zuwa wasu sassan kewaye.