Ọtụtụ ngwa ngwa nke ngwaahịa ụlọ ọrụ, sayensị, na ọgwụ redio (ISM-RF) na-egosi bọọdụ sekit biri ebi okirikiri nhọrọ ukwuu nke ngwaahịa ndị a na -enwekarị ntụpọ dị iche iche.Ndị mmadụ na -achọpụtakarị na otu IC etinyere na bọọdụ sekit abụọ dị iche iche, ihe ngosi arụmọrụ ga -adị iche. Variations in operating conditions, harmonic radiation, anti-interference ability, and start-up time can explain the importance of circuit board layout in a successful design.

This article lists the various design omissions, discusses the causes of each failure, and provides suggestions on how to avoid these design defects. N’ime akwụkwọ a, fr-4 dielectric, 0.0625in ọkpụrụkpụ PCB okpukpu abụọ dịka ọmụmaatụ, bọọdụ sekit na-agbada. Operating in different frequency bands between 315MHz and 915MHz, Tx and Rx power between -120dbm and +13dBm.

Ntụziaka Inductance

Mgbe abụọ inductors (ma ọ bụ ọbụna ahịrị PCB abụọ) nọ ibe ha nso, nkwalite ibe ga -eme. The magnetic field generated by the current in the first circuit excites the current in the second circuit (Figure 1). This process is similar to the interaction between the primary and secondary coils of a transformer. When two currents interact through a magnetic field, the voltage generated is determined by mutual inductance LM:

Ebe, YB bụ voltaji mperi etinyere na sekit B, IA bụ 1 na -arụ ọrụ na sekit A. LM is very sensitive to circuit spacing, inductance loop area (i.e., magnetic flux), and loop direction. Therefore, the best balance between compact circuit layout and reduced coupling is the correct alignment of all inductors in the direction.

FIG. 1. It can be seen from magnetic field lines that mutual inductance is related to inductance alignment direction

The direction of circuit B is adjusted so that its current loop is parallel to the magnetic field line of circuit A. Maka ebumnuche a, dabere na ibe gị, biko rụtụ aka na okirikiri nhọrọ ukwuu nke bọọdụ FSK superheterodyne Receiver Evaluation (EV) (MAX7042EVKIT) (Onyonyo 2). The three inductors on the board (L3, L1 and L2) are very close to each other, and their orientation at 0°, 45° and 90° helps to reduce mutual inductance.

Onyonyo 2. E gosipụtara okirikiri PCB abụọ dị iche iche, otu n’ime ha nwere ihe ndị edoziri n’ụzọ adịghị mma (L1 na L3), ebe nke ọzọ dabara adaba.

To sum up, the following principles should be followed:

Oghere inductance kwesịrị ịdị ka o kwere mee.

A na -ahazi ndị na -etinye ihe nkuku n’akụkụ aka nri iji wedata usoro mkparịta ụka n’etiti ndị na -emepụta ihe.

Duru njikọ ahụ

Dịka ntụzịaka nke ndị na -emepụta ihe na -emetụta njikọta ndọta, otu ahụ ka njikọ ahụ na -emetụta ma ọ bụrụ na ndị ndu dị nso na ibe ha. Ụdị nsogbu okirikiri nhọrọ ukwuu na -emepụtakwa ihe a na -akpọ mmetuta. Otu n’ime nsogbu kacha echegbu nke sekit RF bụ eriri akụkụ ahụ dị nro, dị ka netwọkụ ntinye dabara adaba, ọwa resonant nke onye nnata, netwọkụ kwekọrọ nke eriri nnyefe, wdg.

Ụzọ nloghachi dị ugbu a kwesịrị ịdị nso na isi ụzọ ugbu a ka enwere ike ibelata oghere ndọta radieshon. This arrangement helps to reduce the current loop area. Ụzọ nkwụsị dị mma dị mma maka nloghachi ugbu a na -abụkarị mpaghara ala n’okpuru ndu – na -amachi mpaghara akaghị nke ọma na mpaghara ebe ọkpụrụkpụ nke dielectric na -amụba site n’ogologo ndu. Agbanyeghị, ọ bụrụ na mpaghara ala agbawaa, mpaghara loop na -abawanye (eserese 3). For leads passing through the split region, the return current will be forced through the high resistance path, greatly increasing the current loop area. This arrangement also makes circuit leads more susceptible to mutual inductance.

Ọgụgụ 3. Ntọala nnukwu mpaghara zuru oke na -enyere aka melite arụmọrụ sistemụ

Maka onye nrụpụta n’ezie, ntụzịaka ụzọ na -enwekwa mmetụta dị ukwuu na njikọ ndọta ndọta. Ọ bụrụ na ụzọ nke sekit nwere mmetụta ga -adị ibe ha nso, ọ kacha mma ka hazie ụzọ n’ụzọ kwụ ọtọ iji belata njikọta (Ọgụgụ 4). If vertical alignment is not possible, consider using a guard line. For protection wire design, please refer to the grounding and filling treatment section below.

Figure 4. Similar to Figure 1, shows the possible coupling of magnetic field lines.

To sum up, the following principles should be followed when the plate is distributed:

Complete grounding should be ensured below the lead.

Sensitive leads should be arranged vertically.

If the leads must be arranged in parallel, ensure adequate spacing or use guard wires.

Grounding via

Nsogbu bụ isi na okirikiri okirikiri RF na -abụkarị njiri mara mma nke sekit, gụnyere ihe sekit na njikọta ha. Ndu nwere mkpuchi ọla kọpa dị nhata bụ waya inductance wee mepụta capacitance kesara na ndị ndu ndị ọzọ nọ nso. Ndu ahụ na -egosipụtakwa inductance na ikike capacitance ka ọ na -agafe oghere.

The through-hole capacitance mainly comes from the capacitance formed between the copper cladding on the side of the through-hole pad and the copper cladding on the ground, separated by a fairly small ring. Another influence comes from the cylinder of the metal perforation itself. Mmetụta nke ikike parasitic na-adịkarị obere ma na-ebutekarị mgbanwe ihu na akara dijitalụ dị elu (nke anaghị atụle n’akwụkwọ a).

Mmetụta kasịnụ n’ime oghere bụ parasaiti inductance nke ụdị njikọ njikọ kwekọrọ na ya kpatara. Because most metal perforations in RF PCB designs are the same size as lumped components, the effect of electrical perforations can be estimated using a simple formula (FIG. 5) :

Where, LVIA is lumped inductance through hole; H is the height of the throughhole, in inches; D bụ dayameta nke oghere, na sentimita 2.

Otu esi ezere ntụpọ dị iche iche na nhazi PCB nke mbadamba ebipụta

FIG. 5. PCB cross section used to estimate parasitic effects on through-hole structures

The parasitic inductance often has a great influence on the connection of bypass capacitors. Ndị na-ahụ maka ihe ịga nke ọma na-enye okirikiri dị mkpirikpi ugboro ugboro n’etiti mpaghara ọkọnọ na nhazi, mana oghere na-adịghị mma nwere ike imetụta ụzọ mmetụta dị ala n’etiti nhazi na mpaghara ọkọnọ. A typical PCB through hole (d = 10 mil, h = 62.5 mil) is approximately equivalent to a 1.34nH inductor. N’iburu ugboro ole ngwaahịa ISM-RF na-arụ ọrụ, oghere nwere ike imetụta sekit dị egwu dị ka okirikiri ọwa resonant, ihe nzacha na netwọkụ dabara.

Nsogbu ndị ọzọ na -ebilite ma ọ bụrụ na sekit ndị nwere mmetụta na -ekerịta oghere, dịka ogwe aka abụọ nke netwọkụ ụdị π. Dịka ọmụmaatụ, site n’itinye oghere dị mma nke ya na inductance lumped, atụmatụ nha anya dị nnọọ iche na nhazi sekit mbụ (FIG 6). As with crosstalk of common current path 3, resulting in increased mutual inductance, increased crosstalk and feed-through.

How to avoid PCB design problems

Onyonyo 6. Ọdịdị dị mma vs. ụkpụrụ na-adịghị mma, enwere ike inwe “ụzọ mgbaama” na sekit ahụ.

To sum up, circuit layout should follow the following principles:

Ensure modeling of through-hole inductance in sensitive areas.

The filter or matching network uses independent through-holes.

Note that a thinner PCB copper-clad will reduce the effect of parasitic inductance through the hole.

Na ogologo nke ụzọ

Maxim ISM-RF data ngwaahịa na-atụkarị aro iji ntinye ọsọ ọsọ na nrụpụta dị mkpụmkpụ nwere ike belata mfu na radieshon. N’aka nke ọzọ, ụdị mfu ndị a na-ebutekarị site na paramitic paradaịs na-adịghị mma, yabụ ma inductance na capacitance na-emetụta okirikiri sekit, na iji ụzọ dị mkpụmkpụ enwere ike nyere aka belata parasitic paramiti. Typically, a 10 mil wide PCB lead with a distance of 0.0625in… From a FR4 board produces an inductance of approximately 19nH/in and a distributed capacitance of approximately 1pF/in. Maka okirikiri LAN/ igwekota nwere ihe nrụpụta 20nH na capacitor 3pF, uru akụrụngwa dị irè ga -emetụta nke ukwuu mgbe okirikiri na okirikiri okirikiri dị kọmpat.

Ipc-d-317a4 in ‘Institute for Printed Circuits’ provides an industry standard equation for estimating various impedance parameters of microstrip PCB. Ejiri IPC-2003 2251 dochie akwụkwọ a na 5, nke na-enye usoro mgbako ziri ezi maka ụzọ PCB dị iche iche. Online calculators are available from a variety of sources, most of which are based on equations provided by IPC-2251. The Electromagnetic Compatibility Lab at Missouri Institute of Technology provides a very practical method for calculating PCB lead impedance 6.

The accepted criteria for calculating the impedance of microstrip lines are:

N’ime usoro a, εr bụ ọnụọgụ dielectric nke dielectric, h bụ ịdị elu nke ụzọ site na stratum, W bụ obosara ụzọ, na T bụ ọkpụrụkpụ ụzọ (FIG. 7). Mgbe w/h dị n’agbata 0.1 na 2.0 na isr dị n’agbata 1 na 15, nsonaazụ ngụkọta oge nke usoro a ziri ezi.

Figure 7. This figure is a PCB cross section (similar to Figure 5) and represents the structure used to calculate the impedance of a microstrip line.

In order to evaluate the effect of lead length, it is more practical to determine the detuning effect of ideal circuit by lead parasitical parameters. N’ihe atụ a, anyị na -atụle capacitance na inductance. The standard equation of characteristic capacitance for microstrip lines is:

N’otu aka ahụ, enwere ike ịgbakọ njiri mara njirimara site na akara site na iji akara dị n’elu:

Dịka ọmụmaatụ, were ọkpụrụkpụ PCB nke 0.0625in. (h = 62.5 mil), 1 ounce kpuchiri ọla kọpa (t = 1.35 mil), 0.01in. (w = mil 10), yana bọọdụ FR-4. Rịba ama na ε R nke FR-4 na-abụkarị 4.35 farad/m (F/m), mana ọ nwere ike ịdị site na 4.0F/m ruo 4.7F/m. Eigenvalues ​​gbakọrọ na atụ a bụ Z0 = 134 ω, C0 = 1.04pF/in, L0 = 18.7nH/in.

Maka atụmatụ ISM-RF, ogologo okirikiri okirikiri 12.7mm (0.5in) nwere ike mepụta parasitic paramita ihe dịka 0.5pF na 9.3nH (Onyonyo 8). Mmetụta nke parasitic parameters na ọkwa a na ọwa resonant nke onye nnata (mgbanwe ngwaahịa LC) nwere ike ibute 315MHz ± 2% ma ọ bụ 433.92mhz ± 3.5% mgbanwe. N’ihi mgbakwunye ikike na ntinye nke nsonaazụ parasitic nke ndu, ọnụ ọgụgụ kacha elu nke 315MHz oscillation ruru 312.17mhz, na elu nke 433.92mhz oscillation ugboro ruru 426.6mhz.

Another example is the resonant channel of Maxim’s superheterodyne receiver (MAX7042). The recommended components are 1.2pF and 30nH at 315MHz; At 433.92MHz, it is 0pF and 16nH. Gbakọọ ugboro oscillation nke resonant circuit site na iji akara:

Ntụle nke sekit resonant nke efere kwesịrị ịgụnye mmetụta parasitic nke ngwugwu na nhazi ya, yana parasitic paramita bụ 7.3PF na 7.5PF n’otu n’otu mgbe a na -agbakọ ugboro ugboro resonant 315MHz. Rịba ama na ngwaahịa LC na -anọchite anya capacitor.

Iji chịkọta, a ga -agbaso ụkpụrụ ndị a:

Mee ka ụzọ gị dị nkenke ka o kwere mee.

Debe sekit dị nso na ngwaọrụ ka enwere ike.

A na -akwụ ụgwọ ihe ndị dị mkpa dabere na parasitism okirikiri nhọrọ ukwuu.

Ọgwụ ala na ndochi

The grounding or power layer defines a common reference voltage that supplies power to all parts of the system through a low resistance path. Ịha nhata ọkụ eletrik niile n’ụzọ dị otu a na -arụpụta ezigbo usoro nchekwa.

Direct ugbu a na -emekarị ka ọ na -asọba n’ụzọ dị ala. N’otu aka ahụ, ugbu a na-agbakarị ugboro ugboro ka ọ na-aga n’ụzọ nwere nguzogide kacha ala. So, for a standard PCB microstrip line above the formation, the return current tries to flow into the ground region directly below the lead. As described in the lead coupling section above, the cut ground area introduces various noises that increase crosstalk either through magnetic field coupling or by converging currents (Figure 9).

Otu esi ezere ntụpọ dị iche iche na nhazi PCB nke mbadamba ebipụta

FIG. 9. Keep the formation intact as much as possible, otherwise the return current will cause crosstalk.

Filled ground, also known as guard lines, is commonly used in circuits where continuous grounding is difficult to lay or where shielding sensitive circuits is required (FIG. 10). The shielding effect can be increased by placing grounding holes (i.e. hole arrays) at both ends of the lead or along the lead. 8. Ejikọla eriri nche na ihe ndu e mere iji nye ụzọ nloghachi ugbu a. Nhazi a nwere ike iwebata crosstalk.

Otu esi ezere ntụpọ dị iche iche na nhazi PCB nke mbadamba ebipụta

FIG. 10. Nhazi usoro RF kwesịrị izere wires mkpuchi mkpuchi ọla na -ese n’elu mmiri, ọkachasị ma ọ bụrụ na achọrọ nchacha ọla kọpa.

Ebe ejiri ọla kọpa kpuchie ala (na-ese n’elu mmiri) ma ọ bụ gbanye ya naanị n’otu njedebe, nke na-egbochi ịdị irè ya. In some cases, it can cause unwanted effects by forming parasitic capacitance that changes the impedance of the surrounding wiring or creates a “latent” path between circuits. Na nkenke, ọ bụrụ na etinyere mpempe mkpuchi ọla kọpa (eriri na-abụghị sekit) na bọọdụ sekit iji hụ na ọkpụrụkpụ plating na-agbanwe agbanwe. Ekwesịrị izere mpaghara ejiri ọla kọpa dịka ha na-emetụta nhazi sekit.

N’ikpeazụ, jide n’aka na ị ga -atụle mmetụta mpaghara mpaghara ọ bụla dị nso na antenna. Antenna monopole ọ bụla ga-enwe mpaghara ala, wiring na oghere dị ka akụkụ nke nha sistemụ, yana eriri eriri na-adịghị mma ga-emetụta arụmọrụ radieshon na ntụzịaka nke antenna (template radiation). Therefore, the ground area should not be placed directly below the monopole PCB lead antenna.

To sum up, the following principles should be followed:

Nye mpaghara mpaghara mgbawa na-aga n’ihu ma dịkwa obere ka o kwere mee.

Akwụsịla nsọtụ abụọ nke ahịrị ndochi ahụ, a na-ejikwa oghere dị ka o kwere mee.

Efekwala eriri mkpuchi ọla kọpa dị nso na sekit RF, etinyela ọla kọpa gburugburu sekit RF.

Ọ bụrụ na bọọdụ sekit nwere ọtụtụ ọkwa, ọ kacha mma ịtọba oghere n’ime oghere mgbe eriri mgbaama na -aga site n’otu akụkụ gaa na nke ọzọ.

Oke kristal oke

Parasitic capacitance will cause the crystal frequency to deviate from the target value 9. Yabụ, ekwesịrị ịgbaso ụfọdụ ntuziaka izugbe iji belata ikike kpafuru akpa, mpe mpe akwa, wires, ma ọ bụ njikọ na ngwaọrụ RF.

The following principles should be followed:

Njikọ dị n’etiti ngwa kristal na RF kwesịrị ịdị mkpụmkpụ dị ka o kwere mee.

Keep the wiring from each other as far as possible.

Ọ bụrụ na shunt capacitance capacitor buru oke ibu, wepu mpaghara mgbada n’okpuru kristal.

Planar wiring inductance

Planar wiring or PCB spiral inductors are not recommended. Typical PCB manufacturing processes have certain inaccuracies, such as width and space tolerances, which greatly affect the accuracy of component values. Therefore, most controlled and high Q inductors are wound type. Nke abuo, ị nwere ike họrọ inductor seramiiki multilayer, ndị na -emepụta ihe mgbapụta mgbawa multilayer na -enyekwa ngwaahịa a. Ka o sina dị, ụfọdụ ndị na -emepụta ihe na -ahọrọ ndị na -adọta okirikiri mgbe ha kwesịrị. The standard formula for calculating planar spiral inductance is usually Wheeler’s formula 10:

Ebee, a bụ nkezi radius nke eriri igwe, na sentimita asatọ; N bụ ọnụọgụ ntụgharị; C is the width of the coil core (router-rinner), in inches. Mgbe eriri igwe c “0.2a 11, izi ezi nke usoro ngụkọta oge dị n’ime 5%.

Enwere ike iji ndị na-adọta okirikiri nwere akụkụ anọ, hexagonal, ma ọ bụ ụdị ndị ọzọ. Enwere ike ịchọta ezigbo mgbatị ahụ ka ọ bụrụ ihe atụ maka inductance planar na wafer sekit agbakwunyere. Iji mezuo ebumnuche a, a na -emegharị usoro ọkọlọtọ Wheeler iji nweta usoro ntule inductance ụgbọ elu dabara adaba maka obere nha na nha 12.

Ebee, ρ bụ nha ndochi :; N bụ ọnụ ọgụgụ nke ntụgharị, dAVG bụ nkezi dayameta:. Maka helikopta square, K1 = 2.36, K2 = 2.75.

Enwere ọtụtụ ihe mere ị ga -eji zere iji ụdị inductor a, nke na -ebutekarị mbelata ụkpụrụ inductance n’ihi oke ohere. The main reasons for avoiding planar inductors are limited geometry and poor control of critical dimensions, which makes it impossible to predict inductor values. Na mgbakwunye, ụkpụrụ inductance n’ezie na -esiri ike ịchịkwa n’oge mmepụta PCB, na inductance na -ejikọkwa mkpọtụ n’akụkụ ndị ọzọ nke sekit ahụ.