Anpil aplikasyon ka pwodwi endistriyèl, syantifik, ak medikal frekans radyo (ISM-RF) montre ke la an lèt detache sikwi tablo Layout nan pwodwi sa yo se tendans domaj divès kalite.Moun yo souvan jwenn ke IC a menm enstale sou de tablo sikwi diferan, endikatè pèfòmans yo pral siyifikativman diferan. Variations in operating conditions, harmonic radiation, anti-interference ability, and start-up time can explain the importance of circuit board layout in a successful design.

This article lists the various design omissions, discusses the causes of each failure, and provides suggestions on how to avoid these design defects. Nan papye sa a, fr-4 Dielectric, 0.0625in epesè doub kouch PCB kòm yon egzanp, tablo a sikwi baz. Operating in different frequency bands between 315MHz and 915MHz, Tx and Rx power between -120dbm and +13dBm.

Enduktans direksyon

Lè de enduktè (oswa menm de liy PCB) yo pre youn ak lòt, enduktans mityèl ap fèt. The magnetic field generated by the current in the first circuit excites the current in the second circuit (Figure 1). This process is similar to the interaction between the primary and secondary coils of a transformer. When two currents interact through a magnetic field, the voltage generated is determined by mutual inductance LM:

Ki kote, YB se vòltaj la erè sou fòm piki nan sikwi B, IA se aktyèl la 1 aji sou sikwi A. LM trè sansib a espas sikwi, zòn bouk enduktans (sa vle di, mayetik flux), ak direksyon bouk. Therefore, the best balance between compact circuit layout and reduced coupling is the correct alignment of all inductors in the direction.

FIG. 1. It can be seen from magnetic field lines that mutual inductance is related to inductance alignment direction

The direction of circuit B is adjusted so that its current loop is parallel to the magnetic field line of circuit A. Pou rezon sa a, kòm pèpandikilè ke posib youn ak lòt, tanpri al gade Layout nan sikwi nan ki ba pouvwa FSK superheterodyne reseptè Evalyasyon (EV) tablo a (MAX7042EVKIT) (Figi 2). The three inductors on the board (L3, L1 and L2) are very close to each other, and their orientation at 0°, 45° and 90° helps to reduce mutual inductance.

Figi 2. De diferan Layout PCB yo montre, youn nan ki gen eleman yo ranje nan move direksyon (L1 ak L3), pandan ke lòt la pi apwopriye.

Pou rezime, prensip sa yo ta dwe swiv:

Espas enduktans la ta dwe osi lwen ke posib.

Enduktè yo ranje nan ang dwat pou misyon pou minimize kwaze ant endukteur.

Plon akoupleman an

Menm jan oryantasyon nan enduktè afekte kouple mayetik, se konsa kouple a si kondwi yo twò pre youn ak lòt. Sa a kalite pwoblèm Layout tou pwodwi sa yo rele sansasyon mityèl. Youn nan pwoblèm ki pi konsène nan sikwi RF se fil elektrik la nan pati sansib nan sistèm lan, tankou rezo a matche opinyon, chanèl sonan nan reseptè a, antèn matche rezo nan transmetè a, elatriye.

Retounen chemen aktyèl la ta dwe tankou fèmen nan chemen prensipal aktyèl la ke posib pou minimize radyasyon jaden mayetik. This arrangement helps to reduce the current loop area. Chemen ideyal rezistans ki ba pou retounen aktyèl la anjeneral rejyon tè ki anba plon an – efektivman limite zòn bouk la nan yon rejyon kote epesè dyelèktrik la miltipliye pa longè plon an. Sepandan, si rejyon an tè divize, zòn nan bouk ogmante (Figi 3). For leads passing through the split region, the return current will be forced through the high resistance path, greatly increasing the current loop area. This arrangement also makes circuit leads more susceptible to mutual inductance.

Figi 3. Ranpli baz gwo zòn nan ede amelyore pèfòmans sistèm lan

Pou yon induktè aktyèl, direksyon plon tou gen yon efè enpòtan sou kouple jaden mayetik. Si plon yo nan yon sikwi sansib yo dwe pre youn ak lòt, li pi bon yo aliyen plon yo vètikal diminye kouti (Figi 4). If vertical alignment is not possible, consider using a guard line. Pou konsepsyon fil pwoteksyon, tanpri al gade nan baz la ak ranpli seksyon tretman anba a.

Figure 4. Similar to Figure 1, shows the possible coupling of magnetic field lines.

To sum up, the following principles should be followed when the plate is distributed:

Complete grounding should be ensured below the lead.

Sensitive leads should be arranged vertically.

If the leads must be arranged in parallel, ensure adequate spacing or use guard wires.

Grounding via

Pwoblèm prensipal la ak Layout sikwi RF se anjeneral enpedans nan karakteristik suboptimal nan sikwi a, ki gen ladan eleman yo sikwi ak interconnexions yo. Plon an ak yon kouch kwiv mens ekivalan a fil enduktans epi fòme yon kapasite distribye ak lòt plon nan vwazinaj la. Plon an montre tou pwopriyete enduktans ak kapasite jan li pase nan twou a.

The through-hole capacitance mainly comes from the capacitance formed between the copper cladding on the side of the through-hole pad and the copper cladding on the ground, separated by a fairly small ring. Another influence comes from the cylinder of the metal perforation itself. Efè a nan kapasite parazit se jeneralman ti epi anjeneral sèlman lakòz varyasyon kwen nan gwo vitès siyal dijital (ki pa diskite nan papye sa a).

Pi gwo efè a nan twou a se enduktans nan parazit ki te koze pa mòd nan entèrkonèksyon ki koresponn lan. Because most metal perforations in RF PCB designs are the same size as lumped components, the effect of electrical perforations can be estimated using a simple formula (FIG. 5) :

Where, LVIA is lumped inductance through hole; H is the height of the throughhole, in inches; D se dyamèt twou a, an pous 2.

Ki jan pou fè pou evite divès kalite domaj nan Layout PCB nan tablo enprime

FIG. 5. PCB cross section used to estimate parasitic effects on through-hole structures

The parasitic inductance often has a great influence on the connection of bypass capacitors. Kondansateur kontoune Ideyal bay sikwi segondè-frekans kout ant zòn nan ekipman pou ak fòmasyon an, men ki pa ideyal atravè-twou ka afekte chemen an ki ba-sansiblite ant fòmasyon an ak zòn nan ekipman pou. A typical PCB through hole (d = 10 mil, h = 62.5 mil) is approximately equivalent to a 1.34nH inductor. Etandone frekans fonksyònman espesifik pwodwi ISM-RF la, twou yo ka afekte negativman sikwi sansib tankou sikwi chanèl sonan, filtè, ak rezo matche.

Lòt pwoblèm parèt si sikwi sansib pataje twou, tankou de bra yo nan yon rezo tip π. Pou egzanp, pa mete yon twou ideyal ekivalan a inductance lumped, schematic la ekivalan se byen diferan de konsepsyon sikwi orijinal la (FIG. 6). As with crosstalk of common current path 3, resulting in increased mutual inductance, increased crosstalk and feed-through.

How to avoid PCB design problems

Figi 6. Ideyal vs achitekti ki pa ideyal, gen potansyèl “chemen siyal” nan kous la.

To sum up, circuit layout should follow the following principles:

Ensure modeling of through-hole inductance in sensitive areas.

The filter or matching network uses independent through-holes.

Note that a thinner PCB copper-clad will reduce the effect of parasitic inductance through the hole.

Longè plon an

Done pwodwi Maxim ISM-RF souvan rekòmande pou itilize pi kout posib-wo frekans opinyon ak pwodiksyon mennen pou misyon pou minimize pèt ak radyasyon. Nan lòt men an, pèt sa yo anjeneral ki te koze pa paramèt ki pa ideyal parazit, se konsa tou de enduktans parazit ak kapasite afekte Layout nan sikwi, ak lè l sèvi avèk plon ki pi kout posib ede diminye paramèt yo parazit. Typically, a 10 mil wide PCB lead with a distance of 0.0625in… From a FR4 board produces an inductance of approximately 19nH/in and a distributed capacitance of approximately 1pF/in. Pou yon sikwi LAN / mixer ak yon enduktè 20nH ak yon kondansateur 3pF, valè eleman efikas la pral afekte anpil lè sikwi a ak Layout eleman yo trè kontra enfòmèl ant.

Ipc-d-317a4 in ‘Institute for Printed Circuits’ provides an industry standard equation for estimating various impedance parameters of microstrip PCB. Dokiman sa a te ranplase nan 2003 pa IPC-2251 5, ki bay yon metòd kalkil pi egzak pou plon PCB divès kalite. Online calculators are available from a variety of sources, most of which are based on equations provided by IPC-2251. The Electromagnetic Compatibility Lab at Missouri Institute of Technology provides a very practical method for calculating PCB lead impedance 6.

The accepted criteria for calculating the impedance of microstrip lines are:

Nan fòmil la, εr se konstan dyelèktrik dyelèktrik la, h se wotè plon ki soti nan strat la, W se lajè plon, epi T se epesè plon (FIG. 7). Lè w / h se ant 0.1 ak 2.0 ak εr se ant 1 ak 15, rezilta kalkil fòmil sa a byen egzat.

Figure 7. This figure is a PCB cross section (similar to Figure 5) and represents the structure used to calculate the impedance of a microstrip line.

In order to evaluate the effect of lead length, it is more practical to determine the detuning effect of ideal circuit by lead parasitical parameters. Nan egzanp sa a, nou diskite sou kapasite pèdi ak enduktans. The standard equation of characteristic capacitance for microstrip lines is:

Menm jan an tou, ka enduktans karakteristik la ap kalkile nan ekwasyon an lè l sèvi avèk ekwasyon ki anwo a:

Pou egzanp, asime yon epesè PCB nan 0.0625in. (h = 62.5 mil), 1 ons kòb kwiv mete-kouvwi plon (t = 1.35 mil), 0.01in. (w = 10 mil), ak yon tablo FR-4. Remake byen ke ε R nan FR-4 se tipikman 4.35 farad / m (F / m), men li ka varye ant 4.0F / m 4.7F / m. Valè pwòp yo kalkile nan egzanp sa a se Z0 = 134 ω, C0 = 1.04pF / nan, L0 = 18.7nH / nan.

Pou yon konsepsyon ISM-RF, yon longè Layout 12.7mm (0.5in) nan plon sou tablo a ka pwodwi paramèt parazit nan apeprè 0.5pF ak 9.3nH (Figi 8). Efè paramèt parazit nan nivo sa a sou kanal la sonan nan reseptè a (varyasyon nan pwodwi LC) pouvwa rezilta nan 315MHz ± 2% oswa 433.92mhz ± 3.5% varyasyon. Akòz kapasite adisyonèl la ak enduktans ki te koze pa efè a parazit nan plon an, pik la nan frekans la osilasyon 315MHz rive nan 312.17mhz, ak pikwa nan frekans la osilasyon 433.92mhz rive nan 426.6mhz.

Another example is the resonant channel of Maxim’s superheterodyne receiver (MAX7042). The recommended components are 1.2pF and 30nH at 315MHz; At 433.92MHz, it is 0pF and 16nH. Kalkile frekans nan osilasyon nan sikwi sonan lè l sèvi avèk ekwasyon an:

Evalyasyon kous la sonan nan plak la ta dwe gen ladan efè parazit nan pake a ak Layout a, ak paramèt parazit yo 7.3PF ak 7.5PF respektivman lè yo kalkile frekans sonan 315MHz la. Remake byen ke pwodwi LC la reprezante kapasite kap.

Pou rezime, prensip sa yo dwe swiv:

Kenbe plon an pi kout ke posib.

Mete sikwi kle yo tou pre aparèy la ke posib.

Konpozan kle yo rekonpanse dapre parazitism aktyèl layout.

Terre ak ranpli tretman

The grounding or power layer defines a common reference voltage that supplies power to all parts of the system through a low resistance path. Egalize tout jaden elektrik nan fason sa a pwodui yon bon mekanis pwoteksyon.

Kouran dirèk toujou gen tandans koule sou yon chemen rezistans ki ba. Nan menm fason an, segondè-frekans aktyèl preferansyèlman koule nan chemen an ak rezistans ki pi ba a. So, for a standard PCB microstrip line above the formation, the return current tries to flow into the ground region directly below the lead. As described in the lead coupling section above, the cut ground area introduces various noises that increase crosstalk either through magnetic field coupling or by converging currents (Figure 9).

Ki jan pou fè pou evite divès kalite domaj nan Layout PCB nan tablo enprime

FIG. 9. Keep the formation intact as much as possible, otherwise the return current will cause crosstalk.

Filled ground, also known as guard lines, is commonly used in circuits where continuous grounding is difficult to lay or where shielding sensitive circuits is required (FIG. 10). The shielding effect can be increased by placing grounding holes (i.e. hole arrays) at both ends of the lead or along the lead. 8. Pa melanje fil gad la ak plon ki fèt pou bay yon retou chemen aktyèl la. Aranjman sa a ka prezante kwaze.

Ki jan pou fè pou evite divès kalite domaj nan Layout PCB nan tablo enprime

FIG. 10. Konsepsyon sistèm RF la ta dwe evite k ap flote fil kwiv rekouvèr, espesyalman si se anvlòp kòb kwiv mete yo mande yo.

Zòn nan kòb kwiv mete-rekouvèr pa chita (k ap flote) oswa baz sèlman nan yon sèl fen, ki mete restriksyon sou efikasite li yo. In some cases, it can cause unwanted effects by forming parasitic capacitance that changes the impedance of the surrounding wiring or creates a “latent” path between circuits. Nan ti bout tan, si se yon moso nan CLADDING kwiv (ki pa sikwi fil elektrik siyal) mete sou tablo a sikwi asire yon epesè plating ki konsistan. Yo ta dwe evite zòn kwiv-rekouvèr jan yo afekte konsepsyon sikwi a.

Finalman, asire w ke ou konsidere efè nenpòt zòn tè tou pre antèn lan. Nenpòt antèn monopòl pral gen rejyon tè a, fil elektrik ak twou kòm yon pati nan ekilib sistèm lan, ak fil elektrik ki pa ideyal ap afekte efikasite radyasyon ak direksyon antèn lan (modèl radyasyon). Therefore, the ground area should not be placed directly below the monopole PCB lead antenna.

Pou rezime, prensip sa yo ta dwe swiv:

Bay zòn baz kontinyèl ak ba-rezistans osi lwen ke posib.

Tou de bout liy lan ranpli yo chita, epi yo itilize yon etalaj nan twou osi lwen ke posib.

Pa flote fil kwiv rekouvèr tou pre RF sikwi, pa mete kwiv alantou RF sikwi.

Si tablo sikwi a gen kouch miltip, li pi bon pou mete yon tè nan twou lè kab siyal la pase de yon bò a lòt la.

Kapasite kristal twòp

Parasitic capacitance will cause the crystal frequency to deviate from the target value 9. Se poutèt sa, yo ta dwe swiv kèk direktiv jeneral diminye kapasite pèdi nan broch kristal, kousinen, fil, oswa koneksyon ak aparèy RF.

Prensip sa yo ta dwe swiv:

Koneksyon ki genyen ant kristal la ak aparèy RF yo ta dwe osi kout ke posib.

Kenbe fil elektrik la youn ak lòt osi lwen ke posib.

Si shunt kapasite parazit la twò gwo, retire rejyon an baz anba kristal la.

Plan enductans fil elektrik

Planar wiring or PCB spiral inductors are not recommended. Typical PCB manufacturing processes have certain inaccuracies, such as width and space tolerances, which greatly affect the accuracy of component values. Se poutèt sa, ki pi kontwole ak segondè enduktè Q yo se kalite blesi. Dezyèmman, ou ka chwazi multikouch enduktè seramik, manifaktirè multikouch kondansateur chip tou bay pwodui sa a. Men, kèk konsèpteur chwazi enduktè espiral yo lè yo gen. The standard formula for calculating planar spiral inductance is usually Wheeler’s formula 10:

Ki kote, a se reyon an mwayèn nan bobin la, an pous; N se kantite vire; C se lajè a nan nwayo a bobin (routeur-rinner), an pous. Lè bobin an c “0.2a 11, presizyon nan metòd kalkil la se nan lespas 5%.

Single-kouch enduktè espiral nan fòm kare, egzagonal, oswa lòt ka itilize. Trè bon apwoksimasyon ka jwenn modèl enduktans plan sou gato sikwi entegre. Yo nan lòd yo reyalize objektif sa a, se fòmil la Wheeler estanda modifye yo jwenn yon metòd estimasyon enduktans avyon apwopriye pou ti gwosè ak gwosè kare 12.

Ki kote, ρ se rapò a ranpli :; N se kantite vire, ak dAVG se dyamèt mwayèn :. Pou helices kare, K1 = 2.36, K2 = 2.75.

Gen anpil rezon pou fè pou evite lè l sèvi avèk sa a ki kalite enduktè, ki anjeneral rezilta nan valè enduktans redwi akòz limit espas. The main reasons for avoiding planar inductors are limited geometry and poor control of critical dimensions, which makes it impossible to predict inductor values. Anplis de sa, valè enduktans aktyèl yo difisil pou kontwole pandan pwodiksyon PCB, ak enduktans tou gen tandans fè koup bri nan lòt pati nan kous la.