Plures applicationes causae industrialis, scientificae, et frequentiae radiophonicae medicinae (ISM-RF) productorum ostendunt typis circuitu tabula proclivior ad varios defectus horum productorum asseveratio.Saepe inveniunt eundem IC constitutum in duabus diversis tabulis ambitus, indicibus perficiendis signanter diversum fore. Variations in operating conditions, harmonic radiation, anti-interference ability, and start-up time can explain the importance of circuit board layout in a successful design.

This article lists the various design omissions, discusses the causes of each failure, and provides suggestions on how to avoid these design defects. In charta hac, fr-4 dielectric, 0.0625in crassitudine duplex tabulatum PCB in exemplum, ambitus tabulae fundationis. Operating in different frequency bands between 315MHz and 915MHz, Tx and Rx power between -120dbm and +13dBm.

Inductionem partem

Cum duo inductores (vel etiam duae PCB lineae) inter se appropinquant, mutua inductio occurret. The magnetic field generated by the current in the first circuit excites the current in the second circuit (Figure 1). This process is similar to the interaction between the primary and secondary coils of a transformer. When two currents interact through a magnetic field, the voltage generated is determined by mutual inductance LM:

Ubi, YB est error intentionis injectus in circuitionem B, IA, occurrens 1 agens in circuitu A. LM valde sensilis ad spatium spatii, inductio ansa area (id est, fluxus magneticus), et directio ansa. Therefore, the best balance between compact circuit layout and reduced coupling is the correct alignment of all inductors in the direction.

FIG. 1. It can be seen from magnetic field lines that mutual inductance is related to inductance alignment direction

The direction of circuit B is adjusted so that its current loop is parallel to the magnetic field line of circuit A. Ad hanc rem, quam maxime inter se perpendicularis, quaeso referre ad extensionem superheterodynam receptorem FSK virtutis humilitatis (EV) tabulae (MAX7042EVKIT) (Figura 2). The three inductors on the board (L3, L1 and L2) are very close to each other, and their orientation at 0°, 45° and 90° helps to reduce mutual inductance.

Figura 2. Duae propositiones variae PCB ostenduntur, quarum altera elementa in partem pravam (L1 et L3) disposita sunt, altera vero magis apta.

Ad summam, sequentia principia sunt sequenda.

Inductio spatiorum quantum fieri potest esse debet.

Inductores ad angulos rectos ordinantur ut crosstalk inter inductores minimizet.

Ne coitu

Sicut directio inducentium ad iuncturam magneticam pertinet, ita iunctura ducum si inter se nimis propinqua sunt. Hoc genus quaestionis layout etiam efficit quod sensus mutuus appellatur. Una maxime interest problematum RF circuii partium sensitivarum partium systematis ductarum, ut retis input congruens, canalis recipientis resonantis, antennae retis transmissionis congruens, etc.

Reditus currens debet esse quam proxime ad principale iter currenti quam potest ad extenuando radialem campum magneticum. This arrangement helps to reduce the current loop area. Idealis humilis resistentiae semita pro reditu currenti fere est humus regionis sub plumbo — efficaciter limitando ansam regio ad regionem ubi crassitudo dielectrici per plumbi longitudinem multiplicatur. Tamen, si terra scinditur, ansa area crescit (Figura 3). For leads passing through the split region, the return current will be forced through the high resistance path, greatly increasing the current loop area. This arrangement also makes circuit leads more susceptible to mutual inductance.

Figure 3. Complete magna area præcomprehensio adiuvat amplio ratio perficiendi

Inductor actualis, directio plumbea notabilem vim habet in copulatione campi magnetici. Si ductus ambitus sensitivi esse debent inter se propinqui, optimum est typum ducere perpendiculariter ad coitum reducendum (Figura 4). If vertical alignment is not possible, consider using a guard line. Ad praesidium filum designandum, quaeso refer ad sectionem enucleandam et impletionem curationis infra.

Figure 4. Similar to Figure 1, shows the possible coupling of magnetic field lines.

To sum up, the following principles should be followed when the plate is distributed:

Complete grounding should be ensured below the lead.

Sensitiva ducit directo disponi.

If the leads must be arranged in parallel, ensure adequate spacing or use guard wires.

Grounding via

Problema principale cum RF extensione circuii plerumque est proprium impedimentum circuii suboptimal, incluso in ambitu partium et earum connexionibus. Plumbum tenuissimum efficiens cum inductione filum aeneum aequipollet et formae capacitati distributae cum aliis in vicinia ducit. Plumbum etiam ostendit inductionem et capacitatem possessiones sicut per foramen transit.

The through-hole capacitance mainly comes from the capacitance formed between the copper cladding on the side of the through-hole pad and the copper cladding on the ground, separated by a fairly small ring. Another influence comes from the cylinder of the metal perforation itself. Effectus capacitatis parasiticae est plerumque parvus et plerumque tantum variationem facit in significationibus digitalis summus velocitatis (de quo in hac charta non agitur).

Maximus effectus per-foraminis est inductio parasitica per modum connexionis respondentis causatum. Because most metal perforations in RF PCB designs are the same size as lumped components, the effect of electrical perforations can be estimated using a simple formula (FIG. 5) :

Where, LVIA is lumped inductance through hole; H is the height of the throughhole, in inches; D diametros perforani, pollices II.

Quomodo vitare varios defectus in PCB in layout tabularum impressarum

FIG. 5. PCB cross section used to estimate parasitic effects on through-hole structures

The parasitic inductance often has a great influence on the connection of bypass capacitors. Specimen praetermittunt capacitores summus frequentiam breves circuitus praebent inter zonam copia et formationem, at non-specimen per foramina possunt viam humilem sensibilem inter formationem et zonam copia afficere. A typical PCB through hole (d = 10 mil, h = 62.5 mil) is approximately equivalent to a 1.34nH inductor. Data frequentia specifica producti ISM-RF operantis, per-foramina sensitivas gyros adversare possunt ut gyros, filtra et retiacula congruentia canalis sonantes.

Aliae difficultates oriuntur si circuitus sensitivos foramina communicant, ut duo brachia π – genus reticuli. Exempli gratia, ponendo foramen idealem inductionem coacervatam, aequivalens schismaticum a designatione originis prorsus diversum (FIG. 6). As with crosstalk of common current path 3, resulting in increased mutual inductance, increased crosstalk and feed-through.

How to avoid PCB design problems

Figure 6. Idealis vs architecturae non ideales, sunt potential viae signa in circuitu.

To sum up, circuit layout should follow the following principles:

Ensure modeling of through-hole inductance in sensitive areas.

The filter or matching network uses independent through-holes.

Note that a thinner PCB copper-clad will reduce the effect of parasitic inductance through the hole.

Longitudo plumbi

Maxim ISM-RF producti data saepe commendat utens brevissimo summus frequentia input et output ad damna et radios minuendas ducit. E contra, talia damna fieri solent ex parametris parasiticis non idealibus, ut tam parasitica inductio quam capacitas circa extensionem ambitum afficit, et adhibita brevissima subsidia plumbi parametri parametri ad redigendum. Typically, a 10 mil wide PCB lead with a distance of 0.0625in… From a FR4 board produces an inductance of approximately 19nH/in and a distributed capacitance of approximately 1pF/in. Circuitus enim LAN/mixer cum 20nH inductore et 3pF capacitore, valor componentis effectivus valde afficietur cum ambitus et extensionis componentis valde compacti sunt.

Ipc-d-317a4 in ‘Institute for Printed Circuits’ provides an industry standard equation for estimating various impedance parameters of microstrip PCB. Hoc documentum anno 2003 ab IPC-2251 substitutum est 5, quod accuratiorem calculi methodum pro variis PCB ducit. Online calculators are available from a variety of sources, most of which are based on equations provided by IPC-2251. The Electromagnetic Compatibility Lab at Missouri Institute of Technology provides a very practical method for calculating PCB lead impedance 6.

The accepted criteria for calculating the impedance of microstrip lines are:

In formula, εr dielectric constans est ex dielectric, h est altitudo plumbi ex strato, W latitudo plumbea, T crassitudo plumbea (FIG. 7). Quando w/h est inter 0.1 et 2.0 et εr, est inter 1 et 15, calculus proventus huius formulae satis accurate sunt.

Figure 7. This figure is a PCB cross section (similar to Figure 5) and represents the structure used to calculate the impedance of a microstrip line.

In order to evaluate the effect of lead length, it is more practical to determine the detuning effect of ideal circuit by lead parasitical parameters. In hoc exemplo capacitatem et inductionem errant. The standard equation of characteristic capacitance for microstrip lines is:

Similiter inductio propria computari potest ab aequatione supra aequatione utendo;

Exempli gratia sumatur PCB crassitudinem 0.0625in. uncia plumbi aeris 62.5 (t = 1 mil), 1.35in. (w = 0.01 mil), et FR-10 tabula. Nota ε R ipsius FR-4 proprie esse 4.35 farad /m (F/m), sed ab 4.0F/m ad 4.7F/m proficisci potest. Eigenvales in hoc exemplo computatae sunt Z0 = 134 ω, C0 = 1.04pF/in, L0 = 18.7nH/in.

Pro consilio AN ISM-RF, 12.7mm (0.5in) layout longitudo ducum in tabula potest parametros parasiticos inter 0.5pF et 9.3nH producere (Figura 8). Effectus parametri parasiticorum in hoc gradu in canali sonantis recipientis (variationis LC producti) inveniatur in 315MHz ±2% vel 433.92mhz ±3.5% variatio. Ob accessionem capacitatis et inductionis ex effectu plumbi parasitici, cacumen 315MHz oscillationis frequentia 312.17mhz attingit, et apicem 433.92mhz oscillationis frequentia 426.6mhz attingit.

Another example is the resonant channel of Maxim’s superheterodyne receiver (MAX7042). The recommended components are 1.2pF and 30nH at 315MHz; At 433.92MHz, it is 0pF and 16nH. Computa oscillationem frequentiam circuii resonantis utendo aequatione;

Aestimatio resonantis circa laminae effectus parasiticos fasciculi et extensionis includere debet, et parametri parasitici sunt 7.3PF et 7.5PF respective, cum 315MHz sonorum frequentiam computantes. Nota quod productum LC repraesentat capacitatem coacervatam.

Ad summam, sequentia principia sunt sequenda.

Plumbum quam brevissime serva.

Pone clavem circuli quam proxime machinam quam maxime.

Partes clavis compensantur secundum actualem extensionem parasiti.

Fundamentum et saturitatem curatio

The grounding or power layer defines a common reference voltage that supplies power to all parts of the system through a low resistance path. Adaequans omnes agros electricos hoc modo bonum mechanismum optinet.

Vena directa semper tendit ut per humiliorem viam resistentiae fluat. Ad eundem modum, summus frequentia vena potiore per viam ima resistentia fluit. So, for a standard PCB microstrip line above the formation, the return current tries to flow into the ground region directly below the lead. As described in the lead coupling section above, the cut ground area introduces various noises that increase crosstalk either through magnetic field coupling or by converging currents (Figure 9).

Quomodo vitare varios defectus in PCB in layout tabularum impressarum

FIG. 9. Keep the formation intact as much as possible, otherwise the return current will cause crosstalk.

Filled ground, also known as guard lines, is commonly used in circuits where continuous grounding is difficult to lay or where shielding sensitive circuits is required (FIG. 10). The shielding effect can be increased by placing grounding holes (i.e. hole arrays) at both ends of the lead or along the lead. 8. Noli miscere filum custodiae cum plumbo destinatum ad viam reditus currentem. Haec dispositio crosstalk inducere potest.

Quomodo vitare varios defectus in PCB in layout tabularum impressarum

Fig. 10. RF ratio designandi natandi fila aenea vestita vitare debet, praesertim si vagina aeris exigitur.

Area aenea vestita non nititur vel innititur uno tantum fine, qui suam efficaciam restringit. In some cases, it can cause unwanted effects by forming parasitic capacitance that changes the impedance of the surrounding wiring or creates a “latent” path between circuits. In summa, si fragmentum clasturae aeris (signum non-circuitus wiring) in tabula gyrationis posita sit, ut cohaereat lamina crassitudinis. Areas cupreas vestitas vitandas esse, sicut consilium ambitum afficit.

Denique certo considerare effectus cuiuslibet regionis circa antennas. Antenna quaevis monopolis terram regionem, wiring et foramina aequilibrii systematis partem habebit, et aequilibrium non ideale wiring afficiet antennae efficientiam et directionem radiorum (radiation templates). Therefore, the ground area should not be placed directly below the monopole PCB lead antenna.

Ad summam, sequentia principia sunt sequenda.

Praebebit quantum fieri potest zonis continuam et humilem resistentiam fundandi.

Utraque linea saturitatis fundata est, et per foramen quantum fieri potest ordinata est.

Noli innatare aes filum circa RF ambitum vestitum, noli aes circa RF circuitus ponere.

Si tabula circuii plures ordines continet, optimum est terram per foramen ponere, cum signum funis ab uno latere ad alterum transit.

Nimia crystallis capacitas

Facultas parasiticae efficiet frequentiam cristalli ut deflectat a scopo pretii 9 . Ergo aliquae normae generales sequendae sunt ad redigendum capacitatem cristalli clavi, pads, filis, vel nexus ad RF machinas redigendas.

Quae sequuntur principia sequenda sunt;

Connexio inter crystallum et RF fabrica quam brevissime debet esse.

Wiring se servare quantum potest.

Si capacitas parasitica shunt nimis magna, fundamentum regionis sub crystallo removes.

Planar wiring inductione

Planar wiring or PCB spiral inductors are not recommended. Typical PCB manufacturing processes have certain inaccuracies, such as width and space tolerances, which greatly affect the accuracy of component values. Ideo modestissimi et princeps Q inductores sunt vulnus generis. Secundo, multilayers ceramic inductor eligere potes, multilayer chip capax fabricatores etiam hoc productum praebere. Quidam tamen designantes eligunt gyros inductores cum habent. The standard formula for calculating planar spiral inductance is usually Wheeler’s formula 10:

Ubi, a est radius medius spirae, pollicum; N numero vertil est; C latitudo nuclei spirae (router-riner), in unc. Cum coil c “0.2a 11, accuratio methodi calculi intra 5% est.

Inductores unius spirae strati quadrati, sexangulae, aliaeve figurae adhiberi possunt. approximationes valde bonae inveniri possunt ad exemplar inducentiae planae in ambitu laganae integratae. Ad hoc propositum assequendum, formula Wheeler modificata est ad obtinendam inducta aestimationem planum methodum aptam parvitati quantitati quadratae 12 .

Ubi ρ est ratio impletionis: ; N est numerus rotarum, et dAVG est diameter mediocris. Nam helices quadratae K1 = 2.36, K2 = 2.75.

Multae sunt rationes ad hoc genus inductoris vitandae, quae plerumque consequuntur in valoribus reductis ob limitationes spatii. The main reasons for avoiding planar inductors are limited geometry and poor control of critical dimensions, which makes it impossible to predict inductor values. Praeterea valores actuales inducentes difficiles sunt in productione PCB moderari, et inductio etiam tendit ad strepitum in aliis circuli partibus.