Milandu yambiri yogwiritsira ntchito mafakitale, asayansi, komanso zamankhwala pafupipafupi (ISM-RF) zikuwonetsa kuti bolodi losindikizidwa Kapangidwe kazinthu izi kumakhala zovuta zosiyanasiyana.Anthu nthawi zambiri amawona kuti IC yomweyi idayikidwa pama board awiri osiyana, zizindikilo zantchito zimakhala zosiyana kwambiri. Variations in operating conditions, harmonic radiation, anti-interference ability, and start-up time can explain the importance of circuit board layout in a successful design.

This article lists the various design omissions, discusses the causes of each failure, and provides suggestions on how to avoid these design defects. Mu pepala ili, fr-4 dielectric, 0.0625in makulidwe awiri wosanjikiza PCB monga chitsanzo, dera board lokhazikika. Operating in different frequency bands between 315MHz and 915MHz, Tx and Rx power between -120dbm and +13dBm.

Malangizo othandizira

Ma inductors awiri (kapena mizere iwiri ya PCB) ali pafupi wina ndi mnzake, kulowererana kumachitika. The magnetic field generated by the current in the first circuit excites the current in the second circuit (Figure 1). This process is similar to the interaction between the primary and secondary coils of a transformer. When two currents interact through a magnetic field, the voltage generated is determined by mutual inductance LM:

Komwe, YB ndimagetsi olakwika omwe amalowetsedwa mdera la B, IA ndiye 1 pano yemwe akuchita mdera la A. LM is very sensitive to circuit spacing, inductance loop area (i.e., magnetic flux), and loop direction. Therefore, the best balance between compact circuit layout and reduced coupling is the correct alignment of all inductors in the direction.

FIG. 1. It can be seen from magnetic field lines that mutual inductance is related to inductance alignment direction

The direction of circuit B is adjusted so that its current loop is parallel to the magnetic field line of circuit A. Pachifukwa ichi, mozungulira momwe mungathere, tithandizireni kuyang’anira dera la board low FSK superheterodyne Receiver Evaluation (EV) board (MAX7042EVKIT) (Chithunzi 2). The three inductors on the board (L3, L1 and L2) are very close to each other, and their orientation at 0°, 45° and 90° helps to reduce mutual inductance.

Chithunzi 2. Masanjidwe awiri osiyana a PCB amawonetsedwa, imodzi mwazomwe zili ndi zinthu zomwe zimakonzedwa molakwika (L1 ndi L3), pomwe inayo ndiyabwino.

To sum up, the following principles should be followed:

Kusiyanitsa kwa ma inductance kuyenera kukhala kotheka.

Inductors amakonzedwa pamakona oyenera kuti achepetse crosstalk pakati pa omwe amalowetsa.

Yambani kutsogolera

Monga momwe ma inductors amakhudzira kulumikizana kwa maginito, momwemonso kulumikizana ngati kutsogolera kuli pafupi kwambiri. Mavuto amtunduwu amapanganso zomwe zimatchedwa kutengeka. Limodzi mwa mavuto omwe amakhudzidwa kwambiri ndi dera la RF ndikulumikizana kwa magawo azinthu zovuta, monga kulumikizana kofananira ndi netiweki, njira yolandirira wolandila, neti yolumikizira ma transmitter, ndi zina zambiri.

Njira yobwererera iyenera kukhala yoyandikira kwambiri njira yochepetsera mphamvu yamagetsi yama radiation. This arrangement helps to reduce the current loop area. Njira yotsika yotsika yobwereranso nthawi zambiri nthawi zambiri imakhala gawo locheperako kutsogolera – kumachepetsa bwino malowa kudera lomwe makulidwe a dielectric amachulukitsidwa ndi kutalika kwa kutsogolera. Komabe, ngati gawo lanthaka ligawanika, malo ozungulirawo amakula (Chithunzi 3). For leads passing through the split region, the return current will be forced through the high resistance path, greatly increasing the current loop area. This arrangement also makes circuit leads more susceptible to mutual inductance.

Chithunzi 3. Kukhazikitsa malo okwanira kumathandizira kukonza magwiridwe antchito

Kwa inductor weniweni, lead lead imathandizanso pakulumikiza kwa maginito. Ngati zotsogola zadera loyandikira ziyenera kukhala zoyandikana, ndibwino kulumikizitsa zotsogola kuti muchepetse kulumikizana (Chithunzi 4). If vertical alignment is not possible, consider using a guard line. For protection wire design, please refer to the grounding and filling treatment section below.

Figure 4. Similar to Figure 1, shows the possible coupling of magnetic field lines.

To sum up, the following principles should be followed when the plate is distributed:

Complete grounding should be ensured below the lead.

Sensitive leads should be arranged vertically.

If the leads must be arranged in parallel, ensure adequate spacing or use guard wires.

Grounding via

Vuto lalikulu pakapangidwe kazipangizo za RF nthawi zambiri kumakhala kusokonekera kwa dera, kuphatikiza zigawo zamagawo ndi kulumikizana kwawo. Kutsogolera komwe kuli zokutira kopyapyala mkuwa ndikofanana ndi waya wa inductance ndikupanga capacitance yogawidwa ndi zitsogozo zina kufupi. Kutsogolaku kumawonetsanso kutulutsa ndi kutulutsa mawonekedwe pamene imadutsa dzenje.

The through-hole capacitance mainly comes from the capacitance formed between the copper cladding on the side of the through-hole pad and the copper cladding on the ground, separated by a fairly small ring. Another influence comes from the cylinder of the metal perforation itself. Mphamvu ya parasitic capacitance nthawi zambiri imakhala yaying’ono ndipo nthawi zambiri imangoyambitsa kusiyanasiyana kwamizeremizere yothamanga kwambiri (yomwe sinafotokozedwe papepalali).

Mphamvu yayikulu pakabowo ndikulowerera kwamatenda komwe kumachitika chifukwa cholumikizana molingana. Because most metal perforations in RF PCB designs are the same size as lumped components, the effect of electrical perforations can be estimated using a simple formula (FIG. 5) :

Where, LVIA is lumped inductance through hole; H is the height of the throughhole, in inches; D ndiye m’mimba mwake mwa mainhole 2, mainchesi XNUMX.

Momwe mungapewere zolakwika zosiyanasiyana pakapangidwe ka PCB yamatabwa osindikizidwa

FIG. 5. PCB cross section used to estimate parasitic effects on through-hole structures

The parasitic inductance often has a great influence on the connection of bypass capacitors. Ma capacitors oyenda bwino amapereka maseketi afupipafupi pakati pa malo operekera ndi mapangidwe, koma mabowo osakhala oyenera amatha kukhudza njira yotsika kwambiri pakati pa mapangidwe ndi malo operekera. A typical PCB through hole (d = 10 mil, h = 62.5 mil) is approximately equivalent to a 1.34nH inductor. Popeza mafupipafupi ogwira ntchito a ISM-RF, maenje obowoleza amatha kusokoneza madera azovuta monga ma resonant mayendedwe amakanema, zosefera, ndi ma netiweki ofanana.

Mavuto ena amabwera ngati ma circuits ovuta amagawana mabowo, monga mikono iwiri ya netiweki yamtundu wa π. Mwachitsanzo, poyika bowo lokwanira lofanana ndi lumped inductance, chiwembu chofanana ndichosiyana kwambiri ndi kapangidwe koyambirira koyambira (CHITSANZO. 6). As with crosstalk of common current path 3, resulting in increased mutual inductance, increased crosstalk and feed-through.

How to avoid PCB design problems

Chithunzi 6. Zomangamanga zabwino zotsutsana ndi zomangamanga, pali “njira zazizindikiro” zomwe zingayende.

To sum up, circuit layout should follow the following principles:

Ensure modeling of through-hole inductance in sensitive areas.

The filter or matching network uses independent through-holes.

Note that a thinner PCB copper-clad will reduce the effect of parasitic inductance through the hole.

Kutalika kwa kutsogolera

Zambiri pazogulitsa za Maxim ISM-RF nthawi zambiri zimalimbikitsa kugwiritsa ntchito njira zazifupi kwambiri zotulutsira komanso kutulutsa kumabweretsa kuchepa kwa ma radiation ndi radiation. Kumbali inayi, zotayika zotere zimayambitsidwa ndi ma parasitic omwe siabwino, chifukwa chake kulowerera kwamatenda kumatha kusintha magwiridwe antchito, kugwiritsa ntchito njira yayifupi kwambiri kumathandizira kuchepetsa magawanidwe a parasitic. Typically, a 10 mil wide PCB lead with a distance of 0.0625in… From a FR4 board produces an inductance of approximately 19nH/in and a distributed capacitance of approximately 1pF/in. Pa dera la LAN / chosakanizira chokhala ndi 20nH inductor ndi 3pF capacitor, phindu lothandiziridwalo limakhudzidwa kwambiri maderawo ndi kapangidwe kake zikakhazikika.

Ipc-d-317a4 in ‘Institute for Printed Circuits’ provides an industry standard equation for estimating various impedance parameters of microstrip PCB. Chikalatachi chidasinthidwa mu 2003 ndi IPC-2251 5, chomwe chimapereka njira yowerengera yolondola yazitsogozo zosiyanasiyana za PCB. Online calculators are available from a variety of sources, most of which are based on equations provided by IPC-2251. The Electromagnetic Compatibility Lab at Missouri Institute of Technology provides a very practical method for calculating PCB lead impedance 6.

The accepted criteria for calculating the impedance of microstrip lines are:

Munjira, εr ndiye mawonekedwe a dielectric mosalekeza, h ndiye kutalika kwa kutsogolera kuchokera pa stratum, W ndiye kutsogolera m’lifupi, ndipo T ndiye makulidwe otsogolera (CHITSANZO 7). Pamene w / h ili pakati pa 0.1 ndi 2.0 ndi εr ili pakati pa 1 ndi 15, zotsatira zowerengera za fomuyi ndizolondola.

Figure 7. This figure is a PCB cross section (similar to Figure 5) and represents the structure used to calculate the impedance of a microstrip line.

In order to evaluate the effect of lead length, it is more practical to determine the detuning effect of ideal circuit by lead parasitical parameters. Mu chitsanzo ichi, timakambirana za kusokonekera kwamphamvu ndi kulowerera. The standard equation of characteristic capacitance for microstrip lines is:

Momwemonso, kutengera mawonekedwe kumatha kuwerengedwa kuchokera ku equation pogwiritsa ntchito equation pamwambapa:

Mwachitsanzo, taganizirani kukula kwa PCB kwa 0.0625in. (h = 62.5 mil), 1 ounde wokutidwa ndi mkuwa (t = 1.35 mil), 0.01in. (w = 10 mil), ndi bolodi la FR-4. Dziwani kuti ε R ya FR-4 imakhala 4.35 farad / m (F / m), koma imatha kuyambira 4.0F / m mpaka 4.7F / m. Zowonjezera zomwe zawerengedwa muchitsanzo ichi ndi Z0 = 134 ω, C0 = 1.04pF / in, L0 = 18.7nH / in.

Pakapangidwe ka AN ISM-RF, kutalika kwa 12.7mm (0.5in) kutalika kwa zitsogozo pa bolodi kumatha kupanga magawo aziphuphu pafupifupi 0.5pF ndi 9.3nH (Chithunzi 8). Mphamvu yama parasitic magawo pamlingo wapa resonant wolandila (kusiyanasiyana kwa malonda a LC) atha kubweretsa kusiyana kwa 315MHz ± 2% kapena 433.92mhz ± 3.5%. Chifukwa cha kuchuluka kwa ma capacitance ndi kutayika komwe kumachitika chifukwa chakutitsogolera kwa chiwongolero, chiwongola dzanja cha 315MHz oscillation chimafikira 312.17mhz, ndipo kutalika kwa mafupipafupi a 433.92mhz oscillation kumafika 426.6mhz.

Another example is the resonant channel of Maxim’s superheterodyne receiver (MAX7042). The recommended components are 1.2pF and 30nH at 315MHz; At 433.92MHz, it is 0pF and 16nH. Terengani pafupipafupi oscillation of resonant dera pogwiritsa ntchito equation:

Kuunika kwa dera lokhala ndi mbaleyo kuyenera kuphatikizanso zotsatira za parasitic za phukusi ndi kamangidwe kake, ndipo magawo a parasitic ndi 7.3PF ndi 7.5PF motsatana powerengera mafupipafupi a 315MHz. Dziwani kuti malonda a LC amayimira lumped capacitance.

Mwachidule, mfundo zotsatirazi ziyenera kutsatidwa:

Pitirizani kutsogolera mwachidule momwe mungathere.

Ikani ma circuits ofunikira pafupi ndi chipangizochi momwe zingathere.

Zida zazikuluzikulu zimalipidwa kutengera momwe ziwonetsero zimapangidwira.

Chithandizo chokhazikika komanso chodzaza

The grounding or power layer defines a common reference voltage that supplies power to all parts of the system through a low resistance path. Kufananitsa magawo onse amagetsi munjira imeneyi kumapangitsa njira yabwino yotetezera.

Direct Direct nthawi zonse imakonda kuyenda m’njira yotsika. Momwemonso, mafupipafupi amakono amayenda m’njira ndi kukana kotsika kwambiri. So, for a standard PCB microstrip line above the formation, the return current tries to flow into the ground region directly below the lead. As described in the lead coupling section above, the cut ground area introduces various noises that increase crosstalk either through magnetic field coupling or by converging currents (Figure 9).

Momwe mungapewere zolakwika zosiyanasiyana pakapangidwe ka PCB yamatabwa osindikizidwa

FIG. 9. Keep the formation intact as much as possible, otherwise the return current will cause crosstalk.

Filled ground, also known as guard lines, is commonly used in circuits where continuous grounding is difficult to lay or where shielding sensitive circuits is required (FIG. 10). The shielding effect can be increased by placing grounding holes (i.e. hole arrays) at both ends of the lead or along the lead. 8. Osasakaniza waya wolondera ndi kutsogolera komwe kumapangira njira yobwererera. Makonzedwewa atha kuyambitsa crosstalk.

Momwe mungapewere zolakwika zosiyanasiyana pakapangidwe ka PCB yamatabwa osindikizidwa

CHITH. 10. Kapangidwe ka RF kuyenera kupewa kuyandama zingwe zokutira zamkuwa, makamaka ngati kufunikira kwa mkuwa kukufunika.

Dera lokutidwa ndi mkuwa silikhala pansi (likuyandama) kapena likhazikika kumapeto amodzi, zomwe zimalepheretsa kugwira kwake ntchito. In some cases, it can cause unwanted effects by forming parasitic capacitance that changes the impedance of the surrounding wiring or creates a “latent” path between circuits. Mwachidule, ngati chidutswa chachingwe chachingwe (chosakhudzana ndi zingwe zamagetsi) chikayikidwa pa bolodi lakuwonetsetsa kuti chikula chimakhala cholimba. Madera okutidwa ndi mkuwa ayenera kupewa ngati amakhudza kapangidwe ka dera.

Pomaliza, onetsetsani kuti mukuwona zotsatira za malo aliwonse apafupi ndi tinyanga. Chingwe chilichonse chokhala monopole chimakhala ndi nthaka, zingwe ndi mabowo ngati gawo limodzi, ndipo kulumikizana kosakhala koyenera kumakhudza magwiridwe antchito a radiation ndi ma antenna (radiation template). Therefore, the ground area should not be placed directly below the monopole PCB lead antenna.

To sum up, the following principles should be followed:

Perekani zigawo zosasunthika komanso zotsika kwambiri momwe zingathere.

Malekezero onse a mzere wodzazirayo amakhala pansi, ndipo mzere woboola pakati umagwiritsidwa ntchito momwe zingathere.

Osayandama waya womata wamkuwa pafupi ndi dera la RF, osayika mkuwa mozungulira dera la RF.

Ngati bolodi ladela lili ndi zigawo zingapo, ndibwino kuyala pansi kudzera pa chingwe pomwe chingwe chachizindikiro chimadutsa kuchokera mbali imodzi kupita mbali inayo.

Kugwiritsa galasi capacitance

Parasitic capacitance will cause the crystal frequency to deviate from the target value 9. Chifukwa chake, malangizo ena onse ayenera kutsatidwa kuti achepetse kusokonekera kwa zikhomo zama kristalo, ma pads, mawaya, kapena kulumikizana ndi zida za RF.

The following principles should be followed:

Kulumikizana pakati pa kristalo ndi chida cha RF kuyenera kukhala kochepa momwe zingathere.

Keep the wiring from each other as far as possible.

Ngati shunt parasitic capacitance ndi yayikulu kwambiri, chotsani malo okhala pansi pa kristalo.

Planar wiring inductance

Planar wiring or PCB spiral inductors are not recommended. Typical PCB manufacturing processes have certain inaccuracies, such as width and space tolerances, which greatly affect the accuracy of component values. Therefore, most controlled and high Q inductors are wound type. Kachiwiri, mutha kusankha ma multilayer ceramic inductor, opanga ma multilayer chip capacitor amaperekanso izi. Komabe, opanga ena amasankha olowetsa mwauzimu pomwe akuyenera kutero. The standard formula for calculating planar spiral inductance is usually Wheeler’s formula 10:

Kumene, kuli utali wozungulira wa koyilo, mainchesi; N ndi kuchuluka kosinthana; C ndikukula kwa koyilo koyambira (rauta-rinner), mainchesi. Pamene coil c “0.2a 11, kulondola kwa njira yowerengera ili mkati mwa 5%.

Makina osanjikiza osanjikiza osanjikiza, ozungulira, kapena mawonekedwe ena amatha kugwiritsidwa ntchito. Zolingalira zabwino kwambiri zitha kupezeka pakupanga mapulani a pulaneti pamagulu ophatikizika oyenda. Kuti mukwaniritse cholingachi, mawonekedwe amtundu wa Wheeler amasinthidwa kuti apeze njira yowerengera inductance yoyenera kukula pang’ono ndi kukula kwa 12.

Komwe, ρ ndi chiyerekezo chodzaza :; N ndi chiwerengero chakutembenuka, ndipo dAVG ndiyomwe ili m’mimba mwake :. Pazitsulo zazitali, K1 = 2.36, K2 = 2.75.

Pali zifukwa zambiri zopewera kugwiritsa ntchito mtundu wa inductor, zomwe nthawi zambiri zimabweretsa kutsika kwamalingaliro chifukwa chakuchepa kwa malo. The main reasons for avoiding planar inductors are limited geometry and poor control of critical dimensions, which makes it impossible to predict inductor values. Kuphatikiza apo, kuyerekezera kwenikweni kumakhala kovuta kuwongolera panthawi yopanga PCB, ndipo kutengeka kumathandizanso kuti phokoso likhale lolowera mbali zina zadela.